Texas Instruments CC2650DK ユーザーズマニュアル
AES Cryptoprocessor Overview
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the AAD input data in ext. memory
write DMACH0LEN <length> // AAD data length in bytes, equal to the AAD
// length len({aad data})
// (may be non-block size aligned)
// wait for completion of the AAD data transfer
wait IRQSTAT[1]==’1’// wait for DMA_IN_DONE
check IRQSTAT[31]==‘0’// check for the absence of errors
// configure DMAC
write DMACH0CTL 0x0000_00001 // enable DMA channel 0
write DMACH0EXTADDR <address> // base address of the payload data in ext.
memory
write DMACH0LEN <length> // payload data length in bytes, equal to the message
// length len({crypto_data})
write DMACH1CTL 0x0000_00001 // enable DMA channel 1
write DMACH1EXTADDR <address> // base address of the output data buffer
write DMACH1LEN <length> // output data length in bytes, equal to the result
// data length len({crypto data})
// wait for completion
wait IRQSTAT[0]==’1’// wait for operation completed
check IRQSTAT[31]==‘0’// check for the absence of errors
write ALGSEL 0x0000_0000 // disable the master control/DMA clock
// read tag
wait AESCTL[30]==’1‘ // wait for the SAVED_CONTEXT_RDY bit [30]
read AESTAGOUT__0 - AESTAGOUT__3 // this read clears the ‘saved_context_ready’ flag
// end of algorithm
10.1.6.4 Exceptions Handling
10.1.6.4.1 Soft Reset
If required, the AES module can be forced to abort its current active operation and go into idle state using
the soft reset.
the soft reset.
The idle state means the following:
•
The DMAC is not actively performing DMA operations.
•
The cryptographic modules are in idle state.
•
The key store module does not have any keys loaded.
•
The master control module is in idle state.
•
A soft reset should be executed in the following order:
–
If DMA is used and in operation, it must be stopped.
–
The master control module must be reset via the SWRESET register
•
Write the mode and length registers for the crypto core with zeroes.
The mode and length registers are:
The mode and length registers are:
–
[AESCTL]
–
[AESDATALEN0]
–
[AESDATALEN1]
–
[ AESAUTHLEN]
10.1.6.4.2 External Port Errors
The AHB master interface and the DMAC inside the crypto core can detect AHB port errors received
through the AHB_ERR signal.
through the AHB_ERR signal.
819
SWCU117A – February 2015 – Revised March 2015
Copyright © 2015, Texas Instruments Incorporated