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AES Cryptoprocessor Overview
In this situation, the DMAC disables all channels so that no new transfers are requested, while the error is
captured in the status registers. The [DMAPORTERR] register contains information about the active
channel when the AHB port error occurred. DMAC indicates the channel completion to the master control
module. The recovery procedure is as follows:
captured in the status registers. The [DMAPORTERR] register contains information about the active
channel when the AHB port error occurred. DMAC indicates the channel completion to the master control
module. The recovery procedure is as follows:
•
Issue a soft reset to the DMAC using the [DMASWRESET] register to clear the [DMAPORTERR]
register and initialize the channels to their default state
register and initialize the channels to their default state
•
Issue a soft reset to the master control module to clear its intermediate state.
10.1.6.4.3 Key Store Errors
Key store error generation is implemented for debugging purposes. In normal or specified operation, the
crypto core key store writes and reads should not trigger any errors. A bus error is the only exceptional
case that can result in a key store write error.
crypto core key store writes and reads should not trigger any errors. A bus error is the only exceptional
case that can result in a key store write error.
The key store module checks that the keys are properly written to the key store RAM. When a key write
error occurs, the KEY_ST_WR_ERR flag is asserted in the IRQSTAT register. In this case, the key is not
stored. The host must check the status of the KEY_ST_WR_ERR flag and ensure that the corresponding
RAM area is not used for AES operations.
error occurs, the KEY_ST_WR_ERR flag is asserted in the IRQSTAT register. In this case, the key is not
stored. The host must check the status of the KEY_ST_WR_ERR flag and ensure that the corresponding
RAM area is not used for AES operations.
If, due to software malfunction, the host tries to use a key from a non-written RAM area, the key store
module generates a read error. In this case the KEY_ST_RD_ERR flag is asserted in IRQSTAT. The host
must check the status of this flag and ensure that all remaining steps for the AES operation are not
performed.
module generates a read error. In this case the KEY_ST_RD_ERR flag is asserted in IRQSTAT. The host
must check the status of this flag and ensure that all remaining steps for the AES operation are not
performed.
NOTE:
In case of a read error, the key store writes a key with all bytes set to zero to the AES
engine.
10.1.7 Conventions and Compliances
10.1.7.1 Conventions Used in This Manual
10.1.7.1.1 Acronyms
AES
Advanced Encryption Standard
AES-CCM
AES Counter with CBC-MAC
AHB
Advanced High-speed Bus
AMBA
Advanced Micro-controller Bus Architecture
CBC
Cipher Block Chaining
CCM
Counter with CBC-MAC
CM
Crypto Module
CTR
Counter Mode
DMAC
DMA Controller
DPRAM
Dual port Random Access Memory
ECB
Electronic Code Book
EIP
Embedded Intellectual Property
FIFO
First In First Out
FIPS
Federal Information Processing Standard
GB
Gigabyte
Gbit
Giga bit
Gbps
Giga bits per second
HMAC
Hashed MAC
HW
Hardware
ICM
Integer Counter Mode
IETF
Internet Engineering Task Force
820
SWCU117A – February 2015 – Revised March 2015
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