Microchip Technology ARD00330 データシート

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DS39979A-page 452
Preliminary
 2010 Microchip Technology Inc.
B.5.7
CONTINUOUS COMMUNICATION, 
LOOPING ON ADDRESS SETS
If the user wishes to read back either of the ADC
channels continuously, or both channels continuously,
the internal address counter can be set to loop on spe-
cific register sets. In this case, there is only one control
byte on SDI to start the communication. The part stays
within the same loop until CS returns high.
This internal address counter allows the following
functionality:
• Read one ADC channel data continuously
• Read both ADC channel data continuously (both 
ADC data can be independent or linked with 
DRMODE settings)
• Read continuously the entire register map
• Read continuously each separate register
• Read continuously all Configuration registers
• Write all Configuration registers in one 
communication (see Figure B-11)
The STATUS/COM register contains the loop settings
for the internal address counter (READ<1:0>). The
internal address counter can either stay constant
(READ<1:0> =  00) and read continuously the same
byte, or it can auto-increment and loop through the
register groups defined below (READ<1:0> = 01),
register types (READ<1:0> = 10) or the entire register
map (READ<1:0> = 11). 
Each channel is configured independently as either a
16-bit or 24-bit data word depending on the setting of
the corresponding WIDTH bit in the CONFIG1 register. 
For continuous reading, in the case of WIDTH = 0
(16-bit), the lower byte of the ADC data is not accessed
and the part jumps automatically to the following
address (the user does not have to clock out the lower
byte since it becomes undefined for WIDTH = 0).
The following figure represents a typical, continuous
read communication with the default settings
(DRMODE<1:0> = 00, READ<1:0> = 10) for both width
settings. This configuration is typically used for power
metering applications.
FIGURE B-11: TYPICAL CONTINUOUS READ COMMUNICATION
CH0 ADC 
ADDR/R
CS
SCK
SDI
CH0 ADC 
Upper byte
SDO
CH0 ADC 
Middle byte
CH0 ADC 
Lower byte
DR
CH1 ADC 
Upper byte
CH1 ADC 
Middle byte
CH1 ADC 
Lower byte
CH0 ADC 
Upper byte
CH0 ADC 
Middle byte
CH0 ADC 
Lower byte
CH1 ADC 
Upper byte
CH1 ADC 
Middle byte
CH1 ADC 
Lower byte
These bytes are not present when WIDTH=0 (16-bit mode)