Microchip Technology ARD00330 データシート
2010 Microchip Technology Inc.
Preliminary
DS39979A-page 453
PIC18F87J72 FAMILY
B.5.7.1
Continuous Write
Both ADCs are powered up with their default
configurations and begin to output DR pulses
immediately (RESET<1:0> and SHUTDOWN<1:0>
bits are all ‘0’ by default).
The default output codes for both ADCs are all zeros.
The default modulator output for both ADCs is ‘0011’
(corresponding to a theoretical zero voltage at the
inputs). The default phase is zero between the two
channels.
It is recommended to enter into ADC Reset mode for
both ADCs just after power-up because the desired
register configuration may not be the default one, and
in this case, the ADC would output undesired data.
Within the ADC Reset mode (RESET<1:0> = 11), the
user can configure the whole part with a single commu-
nication. The write commands increment the address
automatically so that the user can start writing the
PHASE register, and finish with the CONFIG2 register,
in only one communication (see Figure B-11). The
RESET<1:0> bits are in the CONFIG2 register to allow
exiting of the Soft Reset mode, and have the whole part
configured and ready to run in only one command.
The following register sets are defined as groups:
configurations and begin to output DR pulses
immediately (RESET<1:0> and SHUTDOWN<1:0>
bits are all ‘0’ by default).
The default output codes for both ADCs are all zeros.
The default modulator output for both ADCs is ‘0011’
(corresponding to a theoretical zero voltage at the
inputs). The default phase is zero between the two
channels.
It is recommended to enter into ADC Reset mode for
both ADCs just after power-up because the desired
register configuration may not be the default one, and
in this case, the ADC would output undesired data.
Within the ADC Reset mode (RESET<1:0> = 11), the
user can configure the whole part with a single commu-
nication. The write commands increment the address
automatically so that the user can start writing the
PHASE register, and finish with the CONFIG2 register,
in only one communication (see Figure B-11). The
RESET<1:0> bits are in the CONFIG2 register to allow
exiting of the Soft Reset mode, and have the whole part
configured and ready to run in only one command.
The following register sets are defined as groups:
The following register sets are defined as types:
B.5.8
SITUATIONS THAT RESET ADC
DATA
DATA
Immediately after the following actions, the ADCs are
temporarily reset in order to provide proper operation:
1.
temporarily reset in order to provide proper operation:
1.
Change in the PHASE register.
2.
Change in the OSR setting.
3.
Change in the PRESCALE setting.
4.
Overwrite of the same PHASE register value.
5.
Change in the CLKEXT bit in the CONFIG2
register, modifying the internal oscillator state.
register, modifying the internal oscillator state.
After these temporary Resets, the ADCs go back to the
normal operation with no need for an additional
command. These are also the settings where the DR
position is affected. The PHASE register can be used
to serially soft reset the ADCs without using the RESET
bits in the Configuration register if the same value is
written in the PHASE register.
normal operation with no need for an additional
command. These are also the settings where the DR
position is affected. The PHASE register can be used
to serially soft reset the ADCs without using the RESET
bits in the Configuration register if the same value is
written in the PHASE register.
FIGURE B-12: RECOMMENDED CONFIGURATION SEQUENCE AT POWER UP
TABLE B-11:
REGISTER GROUPS
GROUP
ADDRESSES
ADC DATA CH0
0x00-0x02
ADC DATA CH1
0x03-0x05
PHASE, GAIN
0x07-0x08
CONFIG, STATUS
0x09-0x0B
TABLE B-12:
REGISTER TYPES
TYPE
ADDRESSES
ADC DATA
(Both Channels)
(Both Channels)
0x00-x05
CONFIGURATION
0x07-0x0B
00011000
CS
SCK
SDI
AV
DD
11XXXXX1
CONFIG2 ADDR/W
CONFIG2
Optional Reset of Both ADCs
One Command for Writing Complete Configuration
PHASE ADDR/W
GAIN
STATUS/COM
CONFIG1
CONFIG2
PHASE
00001110
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