Microchip Technology ARD00330 データシート
PIC18F87J72 FAMILY
DS39979A-page 454
Preliminary
2010 Microchip Technology Inc.
B.5.9
DATA READY PIN (DR)
To signify when channel data is ready for transmission,
the data ready signal is available on the Data Ready pin
(DR) through an active-low pulse at the end of a
channel conversion.
The Data Ready pin outputs an active-low pulse with a
period that is equal to the DRCLK clock period and with
a width equal to one DMCLK period.
When not active-low, this pin can either be in high
impedance (when DR_HIZN = 0) or in a defined logic
high state (when DR_HIZN = 1). This is controlled
through the Configuration registers. This allows multiple
devices to share the same Data Ready pin (with a
pull-up resistor connected between DR and DV
the data ready signal is available on the Data Ready pin
(DR) through an active-low pulse at the end of a
channel conversion.
The Data Ready pin outputs an active-low pulse with a
period that is equal to the DRCLK clock period and with
a width equal to one DMCLK period.
When not active-low, this pin can either be in high
impedance (when DR_HIZN = 0) or in a defined logic
high state (when DR_HIZN = 1). This is controlled
through the Configuration registers. This allows multiple
devices to share the same Data Ready pin (with a
pull-up resistor connected between DR and DV
DD
) in
3-phase energy meter designs to reduce microcontroller
pin count. A single device on the bus does not require a
pull-up resistor.
After a data ready pulse has occurred, the ADC output
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section B.5.9.1 “Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)”).
The CS pin has no effect on the DR pin, which means
even if CS is high, data ready pulses will be provided
(except when the configuration prevents from
outputting data ready pulses). The DR pin can be used
as an interrupt when connected to an external micro-
controller. When the ARESET pin is low, the DR pin is
not active.
pin count. A single device on the bus does not require a
pull-up resistor.
After a data ready pulse has occurred, the ADC output
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section B.5.9.1 “Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)”).
The CS pin has no effect on the DR pin, which means
even if CS is high, data ready pulses will be provided
(except when the configuration prevents from
outputting data ready pulses). The DR pin can be used
as an interrupt when connected to an external micro-
controller. When the ARESET pin is low, the DR pin is
not active.
B.5.9.1
Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)
Ready Modes (DRMODE<1:0>)
To ensure that both channel ADC data are present at
the same time for SPI read, regardless of phase delay
settings for either or both channels, there are two sets
of latches in series with both the data ready and the
‘read start’ triggers.
The first set of latches holds each output when data is
ready and latches both outputs together when
DRMODE<1:0> = 00. When this mode is on, both
ADCs work together and produce one set of available
data after each data ready pulse (that corresponds to
the lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, in order to read the
following ADC output, the current reading needs to be
completed (all bits must be read from the ADC output
data registers).
the same time for SPI read, regardless of phase delay
settings for either or both channels, there are two sets
of latches in series with both the data ready and the
‘read start’ triggers.
The first set of latches holds each output when data is
ready and latches both outputs together when
DRMODE<1:0> = 00. When this mode is on, both
ADCs work together and produce one set of available
data after each data ready pulse (that corresponds to
the lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, in order to read the
following ADC output, the current reading needs to be
completed (all bits must be read from the ADC output
data registers).
B.5.9.2
Data Ready Pin (DR) Control Using
DRMODE Bits
DRMODE Bits
There are four modes that control the data ready
pulses and these modes are set with the
DRMODE<1:0> bits in the STATUS/COM register. For
power metering applications, DRMODE<1:0> = 00 is
recommended (Default mode).
The position of DR pulses vary with respect to this
mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both Data Ready pulses
pulses and these modes are set with the
DRMODE<1:0> bits in the STATUS/COM register. For
power metering applications, DRMODE<1:0> = 00 is
recommended (Default mode).
The position of DR pulses vary with respect to this
mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both Data Ready pulses
from ADC Channel 0 and ADC Channel 1 are
output on the DR pin.
output on the DR pin.
• DRMODE<1:0> = 10: Data Ready pulses from
ADC Channel 1 are output on the DR pin. DR
pulses from ADC Channel 0 are not present on
the pin.
pulses from ADC Channel 0 are not present on
the pin.
• DRMODE<1:0> = 01: Data Ready pulses from
ADC Channel 0 are output on the DR pin. DR
pulses from ADC Channel 1 are not present on
the pin.
pulses from ADC Channel 1 are not present on
the pin.
• DRMODE<1:0> = 00: (Recommended and
Default mode). Data Ready pulses from the
lagging ADC, between the two, are output on the
DR pin. The lagging ADC depends on the PHASE
register and on the OSR. In this mode, the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
lagging ADC, between the two, are output on the
DR pin. The lagging ADC depends on the PHASE
register and on the OSR. In this mode, the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
B.5.9.3
DR Pulses with Shutdown or Reset
Conditions
Conditions
There will be no DR pulses if DRMODE<1:0> = 00
when either one or both of the ADCs are in Reset or
Shutdown. In Mode 00, a DR pulse only happens when
both ADCs are ready. Any DR pulse will correspond to
one data on both ADCs. The two ADCs are linked
together and act as if there was only one channel with
the combined data of both ADCs. This mode is very
practical when both ADC channel data retrieval and
processing need to be synchronized, as in power
metering applications.
when either one or both of the ADCs are in Reset or
Shutdown. In Mode 00, a DR pulse only happens when
both ADCs are ready. Any DR pulse will correspond to
one data on both ADCs. The two ADCs are linked
together and act as if there was only one channel with
the combined data of both ADCs. This mode is very
practical when both ADC channel data retrieval and
processing need to be synchronized, as in power
metering applications.
Figure B-13 represents the behavior of the Data Ready
pin with the different DRMODE and DR_LTY
configurations, while shutdown or Resets are applied.
pin with the different DRMODE and DR_LTY
configurations, while shutdown or Resets are applied.
Note:
If DRMODE<1:0> = 11, the user will still
be able to retrieve the DR pulse for the
ADC not in shutdown or Reset (i.e., only
one ADC channel needs to be awake).
be able to retrieve the DR pulse for the
ADC not in shutdown or Reset (i.e., only
one ADC channel needs to be awake).