Microchip Technology ARD00330 データシート

PIC18F87J72 FAMILY

DS39979A-page 54

Preliminary

 2010 Microchip Technology Inc.

SPBRG2

PIC18F8XJ72

0000 0000

uuuu uuuu

RCREG2

PIC18F8XJ72

0000 0000

uuuu uuuu

TXREG2

PIC18F8XJ72

0000 0000

uuuu uuuu

TXSTA2

PIC18F8XJ72

0000 -010

uuuu -uuu

RCSTA2

PIC18F8XJ72

0000 000x

uuuu uuuu

RTCCFG

PIC18F8XJ72

0-00 0000

u-uu uuuu

RTCCAL

PIC18F8XJ72

0000 0000

uuuu uuuu

RTCVALH

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

RTCVALL

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

ALRMCFG PIC18F8XJ72

0000 0000

uuuu uuuu

ALRMRPT

PIC18F8XJ72

0000 0000

uuuu uuuu

ALRMVALH

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

ALRMVALL

PIC18F8XJ72

xxxx xxxx

uuuu uuuu

CTMUCONH

PIC18F8XJ72

0-00 0000

u-uu uuuu

CTMUCONL

PIC18F8XJ72

0000 0000

uuuu uuuu

CTMUICONH

PIC18F8XJ72

0000 0000

uuuu uuuu

PADCFG1

PIC18F8XJ72

---- -00-

---- -uu-

TABLE 5-2:

INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED)

Register

Applicable

Devices

Power-on Reset,

Brown-out Reset

MCLR Resets

WDT Reset

RESET Instruction

Stack Resets

Wake-up via WDT

or Interrupt

Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition.

Shaded cells indicate conditions do not apply for the designated device.

Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are

updated with the current value of the PC. The STKPTR is modified to point to the next location in the
hardware stack.

2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the

interrupt vector (0008h or 0018h).

3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up).
4: See Table 5-1 for Reset value for specific condition.
5: Bits 6 and 7 of PORTA, LATA and TRISA are enabled depending on the oscillator mode selected. When

not enabled as PORTA pins, they are disabled and read as ‘0’.