Microchip Technology MA240029 データシート

DS39996F-page 158

 2010-2011 Microchip Technology Inc.

Deep Sleep mode provides the lowest levels of power
consumption available from the Instruction-Based
modes.
Deep Sleep modes have these features:
• The system clock source is shut down. If an 

on-chip oscillator is used, it is turned off.

• The device current consumption will be reduced 

to a minimum.

• The I/O pin directions and states are frozen.
• The Fail-Safe Clock Monitor does not operate 

during Sleep mode since the system clock source 
is disabled.

• The LPRC clock will continue to run in Deep 

Sleep mode if the WDT or RTCC with LPRC as 
clock source is enabled.

• The dedicated Deep Sleep WDT and BOR 

systems, if enabled, are used.

• The RTCC and its clock source continue to run, if 

enabled. All other peripherals are disabled.

Entry into Deep Sleep mode is completely under
software control. Exit from the Deep Sleep modes can
be triggered from any of the following events:
• POR event
• MCLR event
• RTCC alarm (If the RTCC is present)
• External Interrupt 0
• Deep Sleep Watchdog Timer (DSWDT) time-out

10.4.1

ENTERING DEEP SLEEP MODE

Deep Sleep mode is entered by setting the DSEN bit in
the DSCON register, and then executing a Sleep
command (PWRSAV #SLEEP_MODE) within one instruc-
tion cycle, to minimize the chance that Deep Sleep will
be spuriously entered.
If the PWRSAV command is not given within one
instruction cycle, the DSEN bit will be cleared by the
hardware and must be set again by the software before
entering Deep Sleep mode. The DSEN bit is also
automatically cleared when exiting Deep Sleep mode. 

The sequence to enter Deep Sleep mode is:
1.

If the application requires the Deep Sleep WDT,
enable it and configure its clock source. For
more information on Deep Sleep WDT, see

2.

If the application requires Deep Sleep BOR,
enable it by programming the DSBOREN
Configuration bit (FDS<6>).

3.

If the application requires wake-up from Deep
Sleep on RTCC alarm, enable and configure the
RTCC module. For more information on RTCC,
see 

4.

If needed, save any critical application context
data by writing it to the DSGPR0 and DSGPR1
registers (optional).

5.

Enable Deep Sleep mode by setting the DSEN
bit (DSCON<15>). 

 

6.

Enter Deep Sleep mode by issuing 3 NOP
commands, and then a PWRSAV #0 instruction.

Any time the DSEN bit is set, all bits in the DSWAKE
register will be automatically cleared.

To re-enter Deep Sleep after a Deep Sleep
wake-up, allow a delay of at least 3 T

CY

after clearing the RELEASE bit.

A repeat sequence is required to set the
DSEN bit. The repeat sequence (repeating
the instruction twice) is required to write
into any of the Deep Sleep registers
(DSCON, DSWAKE, DSGPR0, DSGPR1).
This is required to avoid the user from
entering Deep Sleep by mistake. Any write
to these registers has to be done twice to
actually complete the write (see

Example 1: 

mov #8000, w2

; enable DS

mov w2,  DSCON

mov w2,  DSCON

; second write required to 

actually write to DSCON

Example 2: 

bset 

 DSCON, #15

nop

nop

nop

bset 

 DSCON, #15 ; enable DS (two writes required)