Microchip Technology MA240029 データシート

DS39996F-page 160

 2010-2011 Microchip Technology Inc.

If a MCLR Reset event occurs during Deep Sleep, the
DSGPRx, DSCON and DSWAKE registers will remain
valid, and the RELEASE bit will remain set. The state
of the SOSC will also be retained. The I/O pins,
however, will be reset to their MCLR Reset state. Since
RELEASE is still set, changes to the SOSCEN bit
(OSCCON<1>) cannot take effect until the RELEASE
bit is cleared.
In all other Deep Sleep wake-up cases, application
firmware must clear the RELEASE bit in order to
reconfigure the I/O pins.

10.4.5

DEEP SLEEP WDT

To enable the DSWDT in Deep Sleep mode, program
the Configuration bit, DSWDTEN (CW4<7>). The
device WDT need not be enabled for the DSWDT to
function. Entry into Deep Sleep modes automatically
reset the DSWDT.
The DSWDT clock source is selected by the
DSWDTOSC Configuration bit (CW4<4>). The post-
scaler options are programmed by the DSWDPS<4:0>
Configuration bits (FDS<3:0>). The minimum time-out
period that can be achieved is 1 ms and the maximum is
25.7 days. For more details on the FDS Configuration
register and DSWDT configuration options, refer to 

10.4.5.1

Switching Clocks in Deep Sleep 
Mode

Both the RTCC and the DSWDT may run from either
SOSC or the LPRC clock source. This allows both the
RTCC and DSWDT to run without requiring both the
LPRC and SOSC to be enabled together, reducing
power consumption.
Running the RTCC from LPRC will result in a loss of
accuracy in the RTCC, of approximately 5 to 10%. If a
more accurate RTCC is required, it must be run from
the SOSC clock source. The RTCC clock source is
selected with the RTCOSC Configuration bit (FDS<5>).
Under certain circumstances, it is possible for the
DSWDT clock source to be off when entering Deep
Sleep mode. In this case, the clock source is turned on
automatically (if DSWDT is enabled), without the need
for software intervention. However, this can cause a
delay in the start of the DSWDT counters. In order to
avoid this delay when using SOSC as a clock source,
the application can activate SOSC prior to entering
Deep Sleep mode.

10.4.6

CHECKING AND CLEARING THE 
STATUS OF DEEP SLEEP

Upon entry into Deep Sleep mode, the status bit,
DPSLP (RCON<10>), becomes set and must be
cleared by the software.
On power-up, the software should read this status bit to
determine if the Reset was due to an exit from Deep
Sleep mode, and clear the bit if it is set. Of the four
possible combinations of DPSLP and POR bit states,
three cases can be considered:
• Both the DPSLP and POR bits are cleared. In this 

case, the Reset was due to some event other 
than a Deep Sleep mode exit.

• The DPSLP bit is clear, but the POR bit is set; this 

is a normal POR.

• Both the DPSLP and POR bits are set. This 

means that Deep Sleep mode was entered, the 
device was powered down and Deep Sleep mode 
was exited.

10.4.7

POWER-ON RESETS (PORs)

V

DD

 voltage is monitored to produce PORs. Since

exiting from Deep Sleep mode functionally looks like a
POR, the technique described in 

should be used to distinguish between Deep Sleep and
a true POR event. When a true POR occurs, the entire
device, including all Deep Sleep logic (Deep Sleep
registers, RTCC, DSWDT, etc.) is reset.

This mode represents the lowest power state that the
microcontroller can achieve and still resume operation.
V

BAT

 mode is automatically triggered when the micro-

controller’s main power supply on V

DD

 fails. When this

happens, the microcontroller’s on-chip power switch
connects to a back-up power source, such as a battery,
supplied to the V

BAT

 pin. This maintains a few key

systems at an extremely low-power draw until V

DD

 is

restored.
The power supplied on V

BAT

 only runs two systems: the

RTCC and the Deep Sleep Semaphore registers
(DSGPR0 and DSGPR1). To maintain these systems
during a sudden loss of V

DD

, it is essential to connect a

power source, other than V

DD

 or AV

DD

, to the V

BAT

 pin.