Microchip Technology MA240029 データシート
PIC24FJ128GA310 FAMILY
DS39996F-page 296
2010-2011 Microchip Technology Inc.
FIGURE 24-1:
12-BIT A/D CONVERTER BLOCK DIAGRAM (PIC24FJ128GA310 FAMILY)
Comparator
12-Bit SAR
V
REF
+
DAC
AN22
(1)
AN23
(1)
AN16
(1)
AN21
(1)
AN14
AN15
AN0
AN1
AN2
V
REF
-
Sample Control
S/H
AV
SS
AV
DD
ADC1BUF0:
ADC1BUF25
(2)
AD1CON1
AD1CON2
AD1CON3
AD1CHS
AD1CHITL
AD1CHITH
Control Logic
Data Formatting
Input MUX Control
Conversion Control
Internal Data Bus
16
V
R
+
V
R
-
MU
X
B
V
INH
V
INL
V
INH
V
INH
V
INL
V
INL
V
R
+
V
R
-
V
R
Se
le
ct
V
BG
V
BG
/6
AD1CSSL
AD1CSSH
Note 1:
AN16 through AN23 are implemented on 100-pin devices only.
2:
A/D result buffers are numbered in hexadecimal; ADC1BUF0 through ADC1BUF19 represent Buffers 1 through 26.
CTMU
V
BAT
/2
AV
SS
AV
DD
AD1CON5
V
BG
/2
V
BG
DMA Data Bus
16
AD1CON4
AD1DMBUF
Extended DMA data
Conversion Logic
MU
X
A