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PIC24FJ128GA310 FAMILY
DS39996F-page 68
 2010-2011 Microchip Technology Inc.
TABLE 4-36:
EDS MEMORY ADDRESS WITH DIFFERENT PAGES AND ADDRESSES
4.2.6
SOFTWARE STACK
Apart from its use as a working register, the W15
register in PIC24F devices is also used as a Software
Stack Pointer (SSP). The pointer always points to the
first available free word and grows from lower to higher
addresses. It pre-decrements for stack pops and
post-increments for stack pushes, as shown in
. Note that for a PC push during any CALL
instruction, the MSB of the PC is zero-extended before
the push, ensuring that the MSB is always clear. 
The Stack Pointer Limit Value register (SPLIM), associ-
ated with the Stack Pointer, sets an upper address
boundary for the stack. SPLIM is uninitialized at Reset.
As is the case for the Stack Pointer, SPLIM<0> is
forced to ‘0’ as all stack operations must be
word-aligned. Whenever an EA is generated using
W15 as a source or destination pointer, the resulting
address is compared with the value in SPLIM. If the
contents of the Stack Pointer (W15) and the SPLIM reg-
ister are equal, and a push operation is performed, a
stack error trap will not occur. The stack error trap will
occur on a subsequent push operation. Thus, for
example, if it is desirable to cause a stack error trap
when the stack grows beyond address 2000h in RAM,
initialize the SPLIM with the value, 1FFEh.
Similarly, a Stack Pointer underflow (stack error) trap is
generated when the Stack Pointer address is found to
be less than 0800h. This prevents the stack from
interfering with the SFR space.
A write to the SPLIM register should not be immediately
followed by an indirect read operation using W15.
FIGURE 4-7:
CALL
 STACK FRAME
DSRPAG
(Data Space Read 
Register)
DSWPAG 
(Data Space Write 
Register)
Source/Destination 
Address while 
Indirect 
Addressing
24-Bit EA 
Pointing to EDS
Comment
x
x
0000h to 1FFFh
000000h to 
001FFFh
Near data space
2000h to 7FFFh
002000h to 
007FFFh
001h
001h
8000h to FFFFh
008000h to 
00FFFEh
EPMP memory space
002h
002h
010000h to 
017FFEh
003h




1FFh
003h




1FFh
018000h to 
0187FEh



FF8000h to 
FFFFFEh
000h
000h
Invalid Address
Address error trap
Note 1:
If the source/destination address is below 8000h, the DSRPAG and DSWPAG registers are not considered.
2:
This data space can also be accessed by Direct Addressing.
3:
When the source/destination address is above 8000h and DSRPAG/DSWPAG are ‘0’, an address error 
trap will occur.
Note:
A PC push during exception processing
will concatenate the SRL register to the
MSB of the PC prior to the push.
<Free Word>
PC<15:0>
000000000
0
15
W15 (before CALL)
W15 (after CALL)
S
tac
k Gr
ows T
o
war
ds
H
ig
her
 A
dd
res
s
0000h
PC<22:16>
POP
: [--W15]
PUSH : [W15++]