Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

access type. NWR0 to NWR1 have the same timings and protocol as NWE. In the same way,
NCS represents one of the NCS[0..5] chip select lines.

The read cycle is shown on 

The read cycle starts with the address setting on the memory address bus, i.e.:

{A[23:2], A1, A0} for 8-bit devices

{A[23:2], A1} for 16-bit devices

Figure 15-7. Standard Read Cycle

The NRD signal is characterized by a setup timing, a pulse width, and a hold timing.

1.

NRDSETUP: the NRD setup time is defined as the setup of address before the NRD 
falling edge.

2.

NRDPULSE: the NRD pulse length is the time between NRD falling edge and NRD ris-
ing edge.

3.

NRDHOLD: the NRD hold time is defined as the hold time of address after the NRD ris-
ing edge.

Similarly, the NCS signal can be divided into a setup time, pulse length and hold time.

A[AD_MSB:2]

CLK_SMC

NBS0, NBS1, 

A0, A1

NRD

NCS

D[15:0]

NCSRDSETUP

NRDSETUP

NRDPULSE

NCSRDPULSE

NRDCYCLE

NRDHOLD

NCSRDHOLD