Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート

32072H–AVR32–10/2012

1.

NCSRDSETUP: the NCS setup time is defined as the setup time of address before the 
NCS falling edge.

2.

NCSRDPULSE: the NCS pulse length is the time between NCS falling edge and NCS 
rising edge.

3.

NCSRDHOLD: the NCS hold time is defined as the hold time of address after the NCS 
rising edge.

The NRDCYCLE time is defined as the total duration of the read cycle, i.e., from the time where
address is set on the address bus to the point where address may change. The total read cycle
time is equal to:

Similarly,

All NRD and NCS timings are defined separately for each chip select as an integer number of
CLK_SMC cycles. To ensure that the NRD and NCS timings are coherent, the user must define
the total read cycle instead of the hold timing. NRDCYCLE implicitly defines the NRD hold time
and NCS hold time as:

And,

If null setup and hold parameters are programmed for NRD and/or NCS, NRD and NCS remain
active continuously in case of consecutive read cycles in the same memory (see 

).

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