Atmel Xplained Evaluation Board AT32UC3A3-XPLD AT32UC3A3-XPLD データシート
製品コード
AT32UC3A3-XPLD
186
32072H–AVR32–10/2012
AT32UC3A3
Figure 15-8. No Setup, No Hold on NRD, and NCS Read Signals
• Null Pulse
Programming null pulse is not permitted. Pulse must be at least written to one. A null value leads
to unpredictable behavior.
to unpredictable behavior.
15.6.4.2
Read mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
i n g s t o k n o w w h i c h s i g n a l r i s e s f i r s t . T h e R e a d M o d e b i t i n t h e M O D E r e g i s t e r
(MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS
controls the read operation.
when the read data is available on the data bus. The SMC does not compare NCS and NRD tim-
i n g s t o k n o w w h i c h s i g n a l r i s e s f i r s t . T h e R e a d M o d e b i t i n t h e M O D E r e g i s t e r
(MODE.READMODE) of the corresponding chip select indicates which signal of NRD and NCS
controls the read operation.
•Read is controlled by NRD (MODE.READMODE = 1)
RAM. The read data is available t
PACC
after the falling edge of NRD, and turns to ‘Z’ after the ris-
ing edge of NRD. In this case, the MODE.READMODE bit must be written to one (read is
controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC sam-
ples the read data internally on the rising edge of CLK_SMC that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC sam-
ples the read data internally on the rising edge of CLK_SMC that generates the rising edge of
NRD, whatever the programmed waveform of NCS may be.
CLK_SMC
A[AD_MSB:2]
NBS0, NBS1,
A0, A1
NRD
NCS
D[15:0]
NRDSETUP
NRDPULSE
NCSRDPULSE
NRDCYCLE
NRDCYCLE
NCSRDPULSE
NCSRDPULSE
NRDPULSE
NRDCYCLE