Nxp Semiconductors LPC2917 ユーザーズマニュアル

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

The LPC2917/19 contains four general-purpose I/O ports located at different peripheral 
base addresses. In the 144-pin package all four ports are available. All I/O pins are 
bi-directional, and the direction can be programmed individually. The I/O pad behavior 
depends on the configuration programmed in the port function-select registers.

The key features are:

General-purpose parallel inputs and outputs

Direction control of individual bits

Synchronized input sampling for stable input-data values

All I/O defaults to input at reset to avoid any possible bus conflicts

The general-purpose I/O provides individual control over each bi-directional port pin. 
There are two registers to control I/O direction and output level. The inputs are 
synchronized to achieve stable read-levels.

To generate an open-drain output, set the bit in the output register to the desired value. 
Use the direction register to control the signal. When set to output, the output driver 
actively drives the value on the output: when set to input the signal floats and can be 
pulled up internally or externally.

The five GPIO ports in the LPC2917/19 have the pins listed below. The GPIO pins are 
combined with other functions on the port pins of the LPC2917/19. 

 shows the 

GPIO pins.

 

The GPIO modules are clocked by several clocks, all of which are derived from 
BASE_SYS_CLK; CLK_SYS_PESS and CLK_SYS_GPIOx (x = 0-3), see 

. 

Note that each GPIO has its own CLK__SYS_GPIOx branch clock for power 
management. The frequency of all clocks CLK_SYS_GPIOx is identical to 
CLK_SYS_PESS since they are derived from the same base clock BASE_SYS_CLK.

GPIO0 pin[31:0]

in/out

GPIO port x pins 31 to 0

GPIO1 pin[31:0]

in/out

GPIO port x pins 31 to 0

GPIO2 pin[27:0]

in/out

GPIO port x pins 27 to 0

GPIO3 pin[15:0]

in/out

GPIO port x pins 15 to 0