Nxp Semiconductors LPC2917 ユーザーズマニュアル

LPC2917_19_1

© NXP B.V. 2007. All rights reserved.

Complete LIN 2.0 message handling and transfer

One interrupt per LIN message

Slave response time-out detection

Programmable sync-break length

Automatic sync-field and sync-break generation

Programmable inter-byte space

Hardware or software parity generation

Automatic checksum generation

Fault confinement

Fractional baud-rate generator

The two LIN 2.0 master controllers in the LPC2917/19 have the pins listed below. The LIN 
pins are combined with other functions on the port pins of the LPC2917/19. 

 

shows the LIN pins. For more information see 

 subsection 3.43, LIN master 

controller.

 

The Modulation and Sampling Control Subsystem (MSCSS) in the LPC2917/19 includes 
four Pulse-Width Modulators (PWMs), three10-bit successive approximation 
Analog-to-Digital Converters (ADCs) and two timers.

The key features of the MSCSS are:

Two 10-bit, 400 ksamples/s, 8-channel ADCs with 3.3 V inputs and various trigger- 
start options

Four 6-channel PWMs (Pulse-Width Modulators) with capture and trap functionality

Two dedicated timers to schedule and synchronize the PWMs and ADCs

The MSCSS contains Pulse-Width Modulators (PWMs), Analog-to-Digital Converters 
(ADCs) and timers.

 provides an overview of the MSCSS. An AHB-to-VPB bus bridge takes care of 

communication with the AHB system bus. Two internal timers are dedicated to this 
subsystem. MSCSS timer 0 can be used to generate start pulses for the ADCs and the 
first PWM. The second timer (MSCSS timer 1) is used to generate ‘carrier’ signals for the 
PWMs. These carrier patterns can be used, for example, in applications requiring current 

LIN0/1 TXDL out

LIN channel 0/1 transmit data output

LIN0/1 RXDL in

LIN channel 0/1 receive data input