AMD Am186TMER ユーザーズマニュアル
Interrupt Control Unit
8-4
8.1.2
Interrupt Conditions and Sequence
Interrupts are generally serviced as follows.
8.1.2.1
Nonmaskable Interrupts
Nonmaskable interrupts—the trace interrupt, the NMI interrupt, and software interrupts
(including both user-defined INT statements and software exceptions)—are serviced
regardless of the setting of the interrupt enable flag (IF) in the processor status flags.
(including both user-defined INT statements and software exceptions)—are serviced
regardless of the setting of the interrupt enable flag (IF) in the processor status flags.
8.1.2.2
Maskable Hardware Interrupts
In order for maskable hardware interrupt requests to be serviced, the IF flag must be set
by the STI instruction, and the mask bit associated with each interrupt must be reset.
by the STI instruction, and the mask bit associated with each interrupt must be reset.
8.1.2.3
The Interrupt Request
When an interrupt is requested, the internal interrupt controller verifies that the interrupt is
enabled and that there are no higher priority interrupt requests being serviced or pending.
If the interrupt request is granted, the interrupt controller uses the interrupt type (see Table
8-1) to access a vector from the interrupt vector table.
enabled and that there are no higher priority interrupt requests being serviced or pending.
If the interrupt request is granted, the interrupt controller uses the interrupt type (see Table
8-1) to access a vector from the interrupt vector table.
Each interrupt type has a four-byte vector available in the interrupt vector table. The interrupt
vector table is located in the 1024 bytes from 00000h to 003FFh. Each four-byte vector
consists of a 16-bit offset (IP) value and a 16-bit segment (CS) value. The 8-bit interrupt
type is shifted left 2 bit positions (multiplied by 4) to generate the index into the interrupt
vector table.
vector table is located in the 1024 bytes from 00000h to 003FFh. Each four-byte vector
consists of a 16-bit offset (IP) value and a 16-bit segment (CS) value. The 8-bit interrupt
type is shifted left 2 bit positions (multiplied by 4) to generate the index into the interrupt
vector table.
8.1.2.4
Interrupt Servicing
A valid interrupt transfers execution to a new program location based on the vector in the
interrupt vector table. The next instruction address (CS:IP) and the processor status flags
are pushed onto the stack.
interrupt vector table. The next instruction address (CS:IP) and the processor status flags
are pushed onto the stack.
The interrupt enable flag (IF) is cleared after the processor status flags are pushed on the
stack, disabling maskable interrupts during the interrupt service routine (ISR).
stack, disabling maskable interrupts during the interrupt service routine (ISR).
The segment:offset values from the interrupt vector table are loaded into the code segment
(CS) and the instruction pointer (IP), and execution of the ISR begins.
(CS) and the instruction pointer (IP), and execution of the ISR begins.
8.1.2.5
Returning from the Interrupt
The interrupt return (IRET) instruction pops the processor status flags and the return
address off the stack. Program execution resumes at the point where the interrupt occurred.
address off the stack. Program execution resumes at the point where the interrupt occurred.
The interrupt enable flag (IF) is restored by the IRET instruction along with the rest of the
processor status flags. If the IF flag was set before the interrupt was serviced, interrupts
are re-enabled when the IRET is executed. If there are valid interrupts pending when the
IRET is executed, the instruction at the return address is not executed. Instead, the new
interrupt is serviced immediately.
processor status flags. If the IF flag was set before the interrupt was serviced, interrupts
are re-enabled when the IRET is executed. If there are valid interrupts pending when the
IRET is executed, the instruction at the return address is not executed. Instead, the new
interrupt is serviced immediately.
If an ISR intends to permanently modify the value of any of the saved flags, it must modify
the copy of the Processor Status Flags Register that was pushed onto the stack.
the copy of the Processor Status Flags Register that was pushed onto the stack.