AMD Am186TMER ユーザーズマニュアル

Table 8-1 shows the predefined types and overall priority structure for the Am186ER and 
Am188ER microcontrollers. Nonmaskable interrupts (interrupt types 0–7) are always higher 
priority than maskable interrupts. Maskable interrupts have a programmable priority that 
can override the default priorities relative to one another.

The levels of interrupt priority are as follows:

n

Interrupt priority for nonmaskable interrupts and software interrupts

n

Interrupt priority for maskable hardware interrupts

The nonmaskable interrupts from 00h to 07h and software interrupts (INT instruction) 
always take priority over the maskable hardware interrupts. Within the nonmaskable and 
software interrupts, the trace interrupt has the highest priority, followed by the NMI interrupt, 
followed by the remaining nonmaskable and software interrupts. 

After the trace interrupt and the NMI interrupt, the remaining software exceptions are 
mutually exclusive and can only occur one at a time, so there is no further priority 
breakdown.

Beginning with interrupt type 8 (the Timer 0 interrupt), the maskable hardware interrupts 
have both an overall priority (see Table 8-1) and a programmable priority. The 
programmable priority is the primary priority for maskable hardware interrupts. The overall 
priority is the secondary priority for maskable hardware interrupts.

Because all maskable interrupts are set to a programmable priority of seven on reset, the 
overall priority of the interrupts determines the priority in which each interrupt is granted by 
the interrupt controller until programmable priorities are changed by reconfiguring the 
control registers.

The overall priority levels shown in Table 8-1 are not the same as the programmable priority 
level that is associated with each maskable hardware interrupt. Each of the maskable 
hardware interrupts has a programmable priority from zero to seven, with zero being the 
highest priority (see Table 8-3, “Priority Level,” on page 8-15). 

For example, if the INT4–INT0 interrupts are all changed to programmable priority six and 
no other programmable priorities are changed from the reset value of seven, then the INT4–
INT0 interrupts take precedence over all other maskable interrupts. (Within INT4–INT0, 
INT0 takes precedence over INT1, and INT1 takes precedence over INT2, etc., because 
of the underlying hierarchy of the overall priority.)