Intel i3-2328M マニュアル

目次

• 1 Introduction

  11
  • 1.1 Processor Feature Details

    13
    • 1.1.1 Supported Technologies

      13
  • 1.2 Interfaces

    13
    • 1.2.1 System Memory Support

      13
    • 1.2.2 PCI Express*

      14
    • 1.2.3 Direct Media Interface (DMI)

      15
    • 1.2.4 Platform Environment Control Interface (PECI)

      16
    • 1.2.5 Processor Graphics

      16
    • 1.2.6 Embedded DisplayPort* (eDP)

      17
    • 1.2.7 Intel® Flexible Display Interface (Intel® FDI)

      17
  • 1.3 Power Management Support

    17
    • 1.3.1 Processor Core

      17
    • 1.3.2 System

      17
    • 1.3.3 Memory Controller

      17
    • 1.3.4 PCI Express*

      17
    • 1.3.5 Direct Media Interface (DMI)

      17
    • 1.3.6 Processor Graphics Controller

      18
  • 1.4 Thermal Management Support

    18
  • 1.5 Package

    18
  • 1.6 Terminology

    18
  • 1.7 Related Documents

    20
• 2 Interfaces

  21
  • 2.1 System Memory Interface

    21
    • 2.1.1 System Memory Technology Supported

      21
    • 2.1.2 System Memory Timing Support

      22
    • 2.1.3 System Memory Organization Modes

      22
      • 2.1.3.1 Single-Channel Mode

        22
      • 2.1.3.2 Dual-Channel Mode – Intel® Flex Memory Technology Mode

        22
    • 2.1.4 Rules for Populating Memory Slots

      23
    • 2.1.5 Technology Enhancements of Intel® Fast Memory Access (Intel® FMA)

      24
      • 2.1.5.1 Just-in-Time Command Scheduling

        24
      • 2.1.5.2 Command Overlap

        24
      • 2.1.5.3 Out-of-Order Scheduling

        24
    • 2.1.6 Memory Type Range Registers (MTRRs) Enhancement

      24
    • 2.1.7 Data Scrambling

      24
    • 2.1.8 DRAM Clock Generation

      24
  • 2.2 PCI Express* Interface

    25
    • 2.2.1 PCI Express* Architecture

      25
      • 2.2.1.1 Transaction Layer

        26
      • 2.2.1.2 Data Link Layer

        26
      • 2.2.1.3 Physical Layer

        26
    • 2.2.2 PCI Express* Configuration Mechanism

      27
    • 2.2.3 PCI Express Graphics

      27
    • 2.2.4 PCI Express* Lanes Connection

      28
  • 2.3 Direct Media Interface (DMI)

    28
    • 2.3.1 DMI Error Flow

      28
    • 2.3.2 Processor / PCH Compatibility Assumptions

      28
    • 2.3.3 DMI Link Down

      29
  • 2.4 Processor Graphics Controller (GT)

    29
    • 2.4.1 3D and Video Engines for Graphics Processing

      30
      • 2.4.1.1 3D Engine Execution Units

        30
      • 2.4.1.2 3D Pipeline

        30
      • 2.4.1.3 Video Engine

        31
      • 2.4.1.4 2D Engine

        31
    • 2.4.2 Processor Graphics Display

      32
      • 2.4.2.1 Display Planes

        32
      • 2.4.2.2 Display Pipes

        33
      • 2.4.2.3 Display Ports

        33
      • 2.4.2.4 Embedded DisplayPort*

        33
    • 2.4.3 Intel® Flexible Display Interface (Intel® FDI)

      33
    • 2.4.4 Multi-Graphics Controller Multi-Monitor Support

      34
  • 2.5 Platform Environment Control Interface (PECI)

    34
  • 2.6 Interface Clocking

    34
    • 2.6.1 Internal Clocking Requirements

      34
• 3 Technologies

  35
  • 3.1 Intel® Virtualization Technology (Intel® VT)

    35
    • 3.1.1 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Objectives

      35
    • 3.1.2 Intel® Virtualization Technology (Intel® VT) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) Features

      36
    • 3.1.3 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Objectives

      36
    • 3.1.4 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features

      37
    • 3.1.5 Intel® Virtualization Technology (Intel® VT) for Directed I/O (Intel® VT-d) Features Not Supported

      37
  • 3.2 Intel® Trusted Execution Technology (Intel® TXT)

    38
  • 3.3 Intel® Hyper-Threading Technology (Intel® HT Technology)

    38
  • 3.4 Intel® Turbo Boost Technology

    39
    • 3.4.1 Intel® Turbo Boost Technology Frequency

      39
    • 3.4.2 Intel® Turbo Boost Technology Graphics Frequency

      40
  • 3.5 Intel® Advanced Vector Extensions (Intel® AVX)

    40
  • 3.6 Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI)

    40
    • 3.6.1 PCLMULQDQ Instruction

      41
  • 3.7 Intel® 64 Architecture x2APIC

    41
• 4 Power Management

  43
  • 4.1 Advanced Configuration and Power Interface (ACPI) States Supported

    44
    • 4.1.1 System States

      44
    • 4.1.2 Processor Core / Package Idle States

      44
    • 4.1.3 Integrated Memory Controller States

      44
    • 4.1.4 PCI Express* Link States

      45
    • 4.1.5 Direct Media Interface (DMI) States

      45
    • 4.1.6 Processor Graphics Controller States

      45
    • 4.1.7 Interface State Combinations

      45
  • 4.2 Processor Core Power Management

    46
    • 4.2.1 Enhanced Intel® SpeedStep® Technology

      46
    • 4.2.2 Low-Power Idle States

      47
    • 4.2.3 Requesting Low-Power Idle States

      48
    • 4.2.4 Core C-states

      49
      • 4.2.4.1 Core C0 State

        49
      • 4.2.4.2 Core C1/C1E State

        49
      • 4.2.4.3 Core C3 State

        49
      • 4.2.4.4 Core C6 State

        49
      • 4.2.4.5 Core C7 State

        49
      • 4.2.4.6 C-State Auto-Demotion

        50
    • 4.2.5 Package C-States

      50
      • 4.2.5.1 Package C0

        51
      • 4.2.5.2 Package C1/C1E

        52
      • 4.2.5.3 Package C3 State

        52
      • 4.2.5.4 Package C6 State

        52
      • 4.2.5.5 Package C7 State

        53
      • 4.2.5.6 Dynamic L3 Cache Sizing

        53
  • 4.3 Integrated Memory Controller (IMC) Power Management

    53
    • 4.3.1 Disabling Unused System Memory Outputs

      53
    • 4.3.2 DRAM Power Management and Initialization

      54
      • 4.3.2.1 Initialization Role of CKE

        55
      • 4.3.2.2 Conditional Self-Refresh

        55
      • 4.3.2.3 Dynamic Power-down Operation

        56
      • 4.3.2.4 DRAM I/O Power Management

        56
  • 4.4 PCI Express* Power Management

    56
  • 4.5 Direct Media Interface (DMI) Power Management

    56
  • 4.6 Graphics Power Management

    57
    • 4.6.1 Intel® Rapid Memory Power Management (Intel® RMPM) (also known as CxSR)

      57
    • 4.6.2 Intel® Graphics Performance Modulation Technology (Intel® GPMT)

      57
    • 4.6.3 Graphics Render C-State

      57
    • 4.6.4 Intel® Smart 2D Display Technology (Intel® S2DDT)

      58
    • 4.6.5 Intel® Graphics Dynamic Frequency

      58
    • 4.6.6 Display Power Savings Technology 6.0 (DPST)

      58
    • 4.6.7 Automatic Display Brightness (ADB)

      59
    • 4.6.8 Intel® Seamless Display Refresh Rate Switching Technology (Intel® SDRRS Technology)

      59
  • 4.7 Thermal Power Management

    59
• 5 Thermal Management

  61
  • 5.1 Thermal Design Power (TDP) and Junction Temperature (Tj)

    61
  • 5.2 Thermal Considerations

    61
    • 5.2.1 Intel® Turbo Boost Technology Power Control and Reporting

      62
    • 5.2.2 Package Power Control

      63
    • 5.2.3 Power Plane Control

      63
    • 5.2.4 Turbo Time Parameter

      63
  • 5.3 Thermal and Power Specifications

    64
  • 5.4 Thermal Management Features

    67
    • 5.4.1 Processor Package Thermal Features

      67
      • 5.4.1.1 Adaptive Thermal Monitor

        68
      • 5.4.1.2 Digital Thermal Sensor

        70
      • 5.4.1.3 PROCHOT# Signal

        71
    • 5.4.2 Processor Core Specific Thermal Features

      73
      • 5.4.2.1 On-Demand Mode

        73
    • 5.4.3 Memory Controller Specific Thermal Features

      73
      • 5.4.3.1 Programmable Trip Points

        73
    • 5.4.4 Platform Environment Control Interface (PECI)

      74
      • 5.4.4.1 Fan Speed Control with Digital Thermal Sensor

        74
• 6 Signal Description

  75
  • 6.1 System Memory Interface Signals

    76
  • 6.2 Memory Reference and Compensation Signals

    77
  • 6.3 Reset and Miscellaneous Signals

    78
  • 6.4 PCI Express*-Based Interface Signals

    79
  • 6.5 Embedded DisplayPort* (eDP) Signals

    79
  • 6.6 Intel® Flexible Display Interface (Intel® FDI) Signals

    80
  • 6.7 Direct Media Interface (DMI) Signals

    80
  • 6.8 Phase Lock Loop (PLL) Signals

    80
  • 6.9 Test Access Points (TAP) Signals

    81
  • 6.10 Error and Thermal Protection Signals

    81
  • 6.11 Power Sequencing Signals

    82
  • 6.12 Processor Power Signals

    82
  • 6.13 Sense Signals

    83
  • 6.14 Ground and Non-Critical to Function (NCTF) Signals

    83
  • 6.15 Future Compatibility Signals

    84
  • 6.16 Processor Internal Pull-Up / Pull-Down Resistors

    84
• 7 Electrical Specifications

  85
  • 7.1 Power and Ground Pins

    85
  • 7.2 Decoupling Guidelines

    85
    • 7.2.1 Voltage Rail Decoupling

      85
    • 7.2.2 PLL Power Supply

      85
  • 7.3 Voltage Identification (VID)

    86
  • 7.4 System Agent (SA) VCC VID

    90
  • 7.5 Reserved or Unused Signals

    90
  • 7.6 Signal Groups

    91
  • 7.7 Test Access Port (TAP) Connection

    93
  • 7.8 Storage Condition Specifications

    93
  • 7.9 DC Specifications

    94
    • 7.9.1 Voltage and Current Specifications

      95
  • 7.10 Platform Environmental Control Interface (PECI) DC Specifications

    101
    • 7.10.1 PECI Bus Architecture

      101
    • 7.10.2 PECI DC Characteristics

      102
    • 7.10.3 Input Device Hysteresis

      103
• 8 Processor Pin and Signal Information

  105
  • 8.1 Processor Pin Assignments

    105
  • 8.2 Package Mechanical Information

    155
• 9 DDR Data Swizzling

  167