Motorola MVME5100 사용자 설명서

Registers

http://www.motorola.com/computer/literature

2-71

General Control-Status/Feature Registers

The General Control-Status Register (GCSR) provides miscellaneous
control and status information for the PHB. The bits within the GCSR are
defined as follows:

LEND

Endian Select. If set, the PPC bus is operating in little
endian mode. The PPC address is modified as described in
the section titled

When PPC Devices are Little Endian

page 2-39

. When LEND is clear, the PPC bus is operating

in Big Endian mode, and all data to/from PCI is swapped
as described in the section titled

When PPC Devices are

Big-Endian

on page 2-38

PFBR

PCI Flush Before Read. If set, the PHB guarantees that
all PPC initiated posted write transactions are completed
before any PCI initiated read transactions are allowed to
complete. When PFBR is clear, there is no correlation
between these transaction types and their order of
completion. Refer to the section on Transaction Ordering
for more information.

XMBH

PPC Master Bus Hog. If set, the PPC master of the PHB
operates in the Bus Hog mode. Bus Hog mode means the
PPC Master continually requests the PPC bus for the
entire duration of each transfer.
If Bus Hog is not enabled, the PPC master requests the bus
in a normal manner. Refer to the section titled

PPC

Master

for more information.

Address

$FEFF0008

Bit

0 1 2 3 4 5 6 7 8 9

1
0

1
1

1
2

1
3

1
4

1
5

1
6

1
7

1
8

1
9

2
0

2
1

2
2

2
3

2
4

2
5

2
6

2
7

2
8

2
9

3
0

3
1

Name

GCSR

LEN

PFBR

XFBR

XBT1

XBT0

P64

XID1

XID0

Operation

R/W

Reset