Motorola MVME5100 사용자 설명서
Registers
http://www.motorola.com/computer/literature
2-73
2
PPC Arbiter/PCI Arbiter Control Registers
The PPC Arbiter Register (XARB) provides control and status for the PPC
Arbiter. Refer to the section titled
Arbiter. Refer to the section titled
bits within the XARB register are defined as follows:
FBRx
Flatten Burst Read. This field is used by the PPC Arbiter
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
to control how bus pipelining will be affected after all
burst read cycles. The encoding of this field is shown in
the table below.
FSRx
Flatten Single Read. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat read cycles. The encoding of this field is
shown in the table below.
Arbiter to control how bus pipelining will be affected after
all single beat read cycles. The encoding of this field is
shown in the table below.
FBWx
Flatten Burst Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
Arbiter to control how bus pipelining will be affected after
all burst write cycles. The encoding of this field is shown
in the table below.
FSWx
Flatten Single Write. This field is used by the PPC
Arbiter to control how bus pipelining will be affected after
all single beat write cycles. The encoding of this field is
shown in the table below.
Arbiter to control how bus pipelining will be affected after
all single beat write cycles. The encoding of this field is
shown in the table below.
Address
$FEFF000C
Bit
0 1 2 3 4 5 6 7 8 9
1
0
0
1
1
1
1
2
2
1
3
3
1
4
4
1
5
5
1
6
6
1
7
7
1
8
8
1
9
9
2
0
0
2
1
1
2
2
2
2
3
3
2
4
4
2
5
5
2
6
6
2
7
7
2
8
8
2
9
9
3
0
0
3
1
1
Name
XARB
PARB
FB
R1
R1
FB
R0
R0
FS
R1
R1
FS
R0
R0
FB
W1
W1
FS
W0
W0
FS
W1
W1
FS
W0
W0
PR
I
I
PR
K1
K1
PR
K0
K0
ENA
PR
I1
I1
PR
I0
I0
PR
K3
K3
PR
K2
K2
PR
K1
K1
PR
K0
K0
HIER
2
HIER
1
HIER
0
POL
ENA
Operation
RW
R
RW
RW
RW
R
R
R
R
R
R
R
R
R
R/
W
W
R/
W
W
R/
W
W
R/
W
W
R/
W
W
R/
W
W
R/
W
W
R
R
R/
W
W
R
Reset
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
FBR/FSR/FBW/FSW
Effects on Bus Pipelining
00
None
01
None
10
Flatten always
11
Flatten if switching masters