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National Instruments
DIO 6533
사용자 설명서
National Instruments DIO 6533 사용자 설명서
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Table of Contents
DIO 6533 User Manual
viii
©
National Instruments Corporation
Appendix A
Specifications
Appendix B
Optional Adapter Description
Appendix C
Customer Communication
Glossary
Index
Figures
Figure 1-1.
The Relationship Between the Programming Environment, NI-DAQ,
and Your Hardware ............................................................................... 1-6
Figure 2-1.
DAQCard-6533 Completed Installation................................................ 2-4
Figure 3-1.
PCI-DIO-32HS/PXI-6533 Block Diagram ........................................... 3-2
Figure 3-2.
AT-DIO-32HS Block Diagram ............................................................. 3-3
Figure 3-3.
DAQCard-6533 Block Diagram............................................................ 3-4
Figure 3-4.
Pattern Detection Example .................................................................... 3-7
Figure 4-1.
6533 Device I/O Connector Pin Assignments....................................... 4-2
Figure 4-2.
RTSI Bus Signal Connection ................................................................ 4-9
Figure 4-3.
Example of Data Signal Connections.................................................... 4-11
Figure 4-4.
Transmission Line Terminations........................................................... 4-16
Figure 5-1.
Pattern-Generation Timing.................................................................... 5-1
Figure 5-2.
Internal Request Timing ........................................................................ 5-2
Figure 5-3.
External Request Timing....................................................................... 5-3
Figure 5-4.
Trigger Input Signal Timing.................................................................. 5-4
Figure 5-5.
8255 Emulation Mode Input.................................................................. 5-6
Figure 5-6.
8255 Emulation Mode Output ............................................................... 5-7
Figure 5-7.
8255 Emulation Timing......................................................................... 5-8
Figure 5-8.
Level-ACK Mode Input ........................................................................ 5-10
Figure 5-9.
Level-ACK Mode Output...................................................................... 5-11
Figure 5-10. Level-ACK Mode Input Timing............................................................ 5-12
이전
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