Texas Instruments 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference TPS51206EVM-745 TPS51206EVM-745 데이터 시트
제품 코드
TPS51206EVM-745
TPS1206EVM
DDR2 VTT Sink and Source
Current Transient
Test condition: 5 Vin, VTT = VTTREF = 0.9 V
IVTTREF = 0 A, IVTT Sink and Source
current 1.8 A
IVTTREF = 0 A, IVTT Sink and Source
current 1.8 A
CH1: VTT
CH2: VTTREF
CH3: Transient Clock
TPS1206EVM
DDR3 VTT Sink and Source
Current Transient
Test condition: 5 Vin, VTT = VTTREF = 0.75 V
IVTTREF = 0 A, IVTT Sink and Source
current 1.5 A
IVTTREF = 0 A, IVTT Sink and Source
current 1.5 A
CH1: VTT
CH2: VTTREF
CH3: Transient Clock
Performance Data and Typical Characteristic Curves
7.4
VTT Sink/Source Load Transient
Figure 16. DDR2 (0.9VTT) 1.8-A Sink/Source
Figure 17. DDR3 (0.75VTT) 1.5-A Sink/Source
17
SLUU515
–
August 2011
Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination
Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and
Copyright
©
2011, Texas Instruments Incorporated
DDR4