데이터 시트 (TPS51206EVM-745)차례Using the TPS51206EVM-745, 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR411 Description31.1 Typical Applications31.2 Features32 Electrical Performance Specifications33 Schematics54 Test Setup74.1 Test Equipment74.1.1 Voltage Source74.1.2 Meters74.1.3 Load74.1.4 Oscilloscope74.2 Recommended Wire Gauge74.2.1 VDD dc Source1 to J174.2.2 VLDOIN dc Source2 to J474.2.3 VTT Load to J374.3 Recommended Test Setup75 Configurations85.1 Transient Load Selection85.2 Source Transient Load Selection95.3 Sink Transient Load Selection95.4 S1, S2 Enable Selection96 Test Procedure96.1 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Source Load Regulation96.2 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Sink/Source Current Transient106.3 DDR2 (0.9VTT)/DDR3 (0.75VTT)/DDR3L (0.675VTT)/DDR4 (0.6VTT) Loop Stability Measurement106.4 List of Test Points106.5 Equipment Shutdown117 Performance Data and Typical Characteristic Curves117.1 VTT Load Regulation117.2 VTTREF Load Regulation137.3 VTT Dropout Voltage157.4 VTT Sink/Source Load Transient177.5 DDR3(0.75VTT) S5 Enable Turnon/Turnoff197.6 DDR3 (0.75VTT) S3 Enable Turnon/Turnoff207.7 DDR3 (0.75VTT) Bode Plot218 EVM Assembly Drawing and PCB Layout219 Bill of Materials25Important Notices26크기: 1.25메가바이트페이지: 27Language: English매뉴얼 열기
