Texas Instruments EVM430-F6736 - MSP430F6736 EVM for Metering EVM430-F6736 EVM430-F6736 데이터 시트

1

SD0P0

2

SD0N0

3

SD1P0

4

SD1N0

5

SD2P0

6

SD2N0

7

VREF

8

AVSS

9

AVCC

10

VASYS

11

P1.0/PM_TA0.0/VeREF-/A2

12

P1.1/PM_TA0.1/VeREF+/A1

13

P1.2/PM_UCA0RXD/PM_UCA0SOMI/A0

14

P1.3/PM_UCA0TXD/PM_UCA0SIMO/R03

15

AUXVCC2

16

AUXVCC1

17

VDSYS

18

DVCC

19

DVSS

20

VCORE

21

XIN

22

XOUT

23

AUXVCC3

24

P1.4/PM_UCA1RXD/PM_UCA1SOMI/LCDREF/R13

25

P1.5/PM_UCA1TXD/PM_UCA1SIMO/R23

26

LCDCAP/R33

27

COM0

28

COM1

29

COM2

30

COM3

31

P1.6/PM_UCA0CLK/COM4

32

P1.7/PM_UCB0CLK/COM5

33

P2.0/PM_UCB0SOMI/PM_UCB0SCL/COM6/S39

34

P2.1/PM_UCB0SIMO/PM_UCB0SDA/COM7/S38

35

P2.2/PM_UCA2RXD/PM_UCA2SOMI/S37

36

P2.3/PM_UCA2TXD/PM_UCA2SIMO/S36

37

P2.4/PM_UCA1CLK/S35

38

P2.5/PM_UCA2CLK/S34

39

P2.6/PM_T

A1.0/S33

40

P2.7/PM_T

A1.1/S32

41

P3.0/PM_TA2.0/S31/BSL_TX

42

P3.1/PM_TA2.1/S30/BSL_RX

43

P3.2/PM_TACLK/PM_RTCCLK/S29

44

P3.3/PM_TA0.2/S28

45

P3.4/PM_SDCLK/S27

46

P3.5/PM_SD0DIO/S26

47

P3.6/PM_SD1DIO/S25

48

P3.7/PM_SD2DIO/S24

49

P4.0/S23

50

P4.1/S22

51

P4.2/S21

52

P4.3/S20

53

P4.4/S19

54

P4.5/S18

55

P4.6/S17

56

P4.7/S16

57

P5.0/S15

58

P5.1/S14

59

DVSYS

60

DVSS

61

P5.2/S13

62

P5.3/S12

63

P5.4/S1

1

64

P5.5/S10

65

P5.6/S9

66

P5.7/S8

67

P6.0/S7

68

P6.1/S6

69

P6.2/S5

70

P6.3/S4

71

P6.4/S3

72

P6.5/S2

73

P6.6/S1

74

P6.7/S0

75

TEST/SBWTCK

76

PJ.0/SMCLK/TDO

77

PJ.1/MCLK/TDI/TCLK

78

PJ.2/ADC10CLK/TMS

79

PJ.3/ACLK/TCK

80

RST/NMI/SBWTDIO

SLAS731C – DECEMBER 2011 – REVISED FEBRUARY 2013

NOTE: The secondary digital functions on Ports P1, P2, and P3 are fully mappable. The pin designation shows the default

mapping. See

for details.

NOTE: The pins VDSYS and DVSYS must be connected externally on board for proper device operation.

CAUTION: The LCDCAP/R33 pin must be connected to DVSS if not used.

Copyright © 2011–2013, Texas Instruments Incorporated

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