Texas Instruments TMS320C6472 Evaluation Module TMDSEVM6472LE TMDSEVM6472LE 데이터 시트
제품 코드
TMDSEVM6472LE
PRODUCTPREVIEW
SPRS612G
–
JUNE 2009
–
REVISED JULY 2011
Table 7-32. PLL2 Stabilization, Lock, and Reset Times
MIN
TYP
MAX
UNIT
PLL2 stabilization time
500
μ
s
PLL2 lock time
2000 * C
(1)
ns
PLL2 reset time
128 * C
(1)
ns
(1)
C = CLKIN2 cycle time in ns. For example, when CLKIN2 frequency is 25 MHz, use C = 40 ns.
7.9.2
PLL2 Controller Peripheral Register Descriptions
The memory map of the PLL2 controller is shown in
. Note that only registers documented here
are accessible on the C6472. Other addresses in the PLL2 controller memory map should not be
modified.
modified.
Table 7-33. PLL2 Controller Registers
HEX ADDRESS RANGE
ACRONYM
REGISTER NAME
029C 0000
PID
Constant Peripheral Identification Register
029C 0004 - 029C 00FC
-
Reserved
029C 0100
PLLCTL
PLL Control Register
029C 0104 - 029C 0114
-
Reserved
029C 0118
PLLDIV1
PLL Controller Divider 1 Register for SYSCLK13
029C 011C
PLLDIV2
PLL Controller Divider 2 Register for SYSCLK14
029C 0120
PLLDIV3
PLL Controller Divider 3 Register for SYSCLK15
029C 0124 - 029C 0134
-
Reserved
029C 0138
PLLCMD
PLL Controller Command Register
029C 013C
PLLSTAT
PLL Controller Status Register
029C 0140
-
Reserved
029C 0144
DCHANGE
PLLDIV Ratio Change Status Register
029C 0148 - 029C 014C
-
Reserved
029C 0150
SYSTAT
SYSCLK Status Register
029C 0154 - 029C 015C
-
Reserved
029C 0160
PLLDIV4
PLL Controller Divider 4 Register for SYSCLK16
029C 0164
PLLDIV5
PLL Controller Divider 5 Register for SYSCLK17
029C 0168
PLLDIV6
PLL Controller Divider 6 Register for SYSCLK18
029C 016C - 029C 03FC
-
Reserved
Copyright
©
2009
–
2011, Texas Instruments Incorporated
C64x+ Peripheral Information and Electrical Specifications
163
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