Texas Instruments DLP Flex Cables DLP5500FLEX DLP5500FLEX 데이터 시트
제품 코드
DLP5500FLEX
SCTRL_AN
SCTRL_AP
D_AN(15:0)
D_AP(15:0)
D_BN(15:0)
D_BP(15:0)
DCLK_BN
DCLK_BP
SCTRL_BN
SCTRL_BP
DCLK_AN
DCLK_AP
T
w
Tc
T
w
Th
Th
Ts
Ts
Tsk
e
w
T
w
Tc
T
w
Th
Th
Ts
Ts
DLPS013E – APRIL 2010 – REVISED SEPTEMBER 2013
SWITCHING CHARACTERISTICS
over operating free-air temperature range (unless otherwise noted)
LVDS TIMING PARAMETERS
MIN
NOM
MAX
UNIT
See
t
c
Clock Cycle DLCK_A or DCLKC_B
4.0
ns
t
w
Pulse Width DCLK_A or DCLK_B
1.25
ns
t
s
Setup Time, D_A[0:15] before DCLK_A
.35
ns
t
s
Setup Time, D_B[0:15] before DCLK_B
.35
ns
t
h
Hold Time, D_A[0:15] after DCLK_A
.35
ns
t
h
Hold Time, D_B[0:15] after DCLK_B
.35
ns
t
skew
Channel B relative to Channel A
-1.25
1.25
ns
LVDS Waveform Requirements
See
|V
ID
|
Input Differential Voltage (absolute difference)
100
400
600
mV
V
CM
Common Mode Voltage
1200
mV
V
LVDS
LVDS Voltage
0
2000
mV
t
r
Rise Time (20% to 80%)
100
400
ps
t
r
Fall Time (80% to 20%)
100
400
ps
Serial Control Bus Timing Parameters
See
and
f
SCP_CLK
SCP Clock Frequency
50
500
KHz
t
SCP_SKEW
Time between valid SCP_DI and rising edge of SCP_CLK
-300
300
ns
t
SCP_DELAY
Time between valid SCP_DO and rising edge of SCP_CLK
2600
ns
Time between falling edge of SCP_EN and the first rising edge of
t
SCP_EN
30
ns
SCP_CLK
t
r_SCP
Rise time for SCP signals
200
ns
t
fP
Fall time for SCP signals
200
ns
Figure 9. LVDS Timing Waveforms
Copyright © 2010–2013, Texas Instruments Incorporated
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