Texas Instruments DLP Flex Cables DLP5500FLEX DLP5500FLEX 데이터 시트
제품 코드
DLP5500FLEX
SCP_CLK
SCP_DI
t
SCP_SKEW
SCP_DO
t
SCP_DELAY
t
SCP_ENZ
SCP_EN
V
/2
CC
0 v
SCP_CLK,
SCP_DI,
SCP_EN
SCP_DI,
SCP_EN
Input Controller V
CC
t
r_SCP
t
f_SCP
V
CM
V
LVDS
(v)
V
ID
T
r
(20% - 80%)
T
f
(20% - 80%)
Time
V
LVDSmax
V
LVDS min
V
= V
+ |½V |
ID
LVDSmax
CM
V
LVDS
= V
CM
+/- | 1/2 V
ID
|
V
LVDS min
= 0
DLPS013E – APRIL 2010 – REVISED SEPTEMBER 2013
Figure 10. LVDS Waveform Requirements
Figure 12. Serial Communications Bus Waveform
Requirements
Figure 11. Serial Communications Bus Timing
Parameters
DMD Power-Up and Power-Down Procedures
Repeated failure to adhere to the prescribed power-up and power-down procedures may affect device reliability.
The DLP5500 power-up and power-down procedures are defined by the DLPC200 Datasheet (TI Literature
number
The DLP5500 power-up and power-down procedures are defined by the DLPC200 Datasheet (TI Literature
number
) and the .55 XGA Chipset Datasheet (TI Literature number
). These procedures must
be followed to ensure reliable operation of the device.
16
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