Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트

Texas Instruments

제품 코드

DK-TM4C129X

Table 2-13. Cortex-M4F Instruction Summary (continued)

Flags

Brief Description

Operands

Mnemonic

-

Compare and branch if zero

Rn, label

CBZ

-

Clear exclusive

-

CLREX

-

Count leading zeros

Rd, Rm

CLZ

N,Z,C,V

Compare negative

Rn, Op2

CMN

N,Z,C,V

Compare

Rn, Op2

CMP

-

Change processor state, disable
interrupts

i

CPSID

-

Change processor state, enable
interrupts

i

CPSIE

-

Data memory barrier

-

DMB

-

Data synchronization barrier

-

DSB

N,Z,C

Exclusive OR

{Rd,} Rn, Op2

EOR, EORS

-

Instruction synchronization barrier

-

ISB

-

If-Then condition block

-

IT

-

Load multiple registers, increment after

Rn{!}, reglist

LDM

-

Load multiple registers, decrement
before

Rn{!}, reglist

LDMDB, LDMEA

-

Load multiple registers, increment after

Rn{!}, reglist

LDMFD, LDMIA

-

Load register with word

Rt, [Rn, #offset]

LDR

-

Load register with byte

Rt, [Rn, #offset]

LDRB, LDRBT

-

Load register with two bytes

Rt, Rt2, [Rn, #offset]

LDRD

-

Load register exclusive

Rt, [Rn, #offset]

LDREX

-

Load register exclusive with byte

Rt, [Rn]

LDREXB

-

Load register exclusive with halfword

Rt, [Rn]

LDREXH

-

Load register with halfword

Rt, [Rn, #offset]

LDRH, LDRHT

-

Load register with signed byte

Rt, [Rn, #offset]

LDRSB, LDRSBT

-

Load register with signed halfword

Rt, [Rn, #offset]

LDRSH, LDRSHT

-

Load register with word

Rt, [Rn, #offset]

LDRT

N,Z,C

Logical shift left

Rd, Rm, <Rs|#n>

LSL, LSLS

N,Z,C

Logical shift right

Rd, Rm, <Rs|#n>

LSR, LSRS

-

Multiply with accumulate, 32-bit result

Rd, Rn, Rm, Ra

MLA

-

Multiply and subtract, 32-bit result

Rd, Rn, Rm, Ra

MLS

N,Z,C

Move

Rd, Op2

MOV, MOVS

N,Z,C

Move 16-bit constant

Rd, #imm16

MOV, MOVW

-

Move top

Rd, #imm16

MOVT

-

Move from special register to general
register

Rd, spec_reg

MRS

N,Z,C,V

Move from general register to special
register

spec_reg, Rm

MSR

N,Z

Multiply, 32-bit result

{Rd,} Rn, Rm

MUL, MULS

N,Z,C

Move NOT

Rd, Op2

MVN, MVNS

-

No operation

-

NOP

N,Z,C

Logical OR NOT

{Rd,} Rn, Op2

ORN, ORNS

December 13, 2013

138

Texas Instruments-Advance Information

The Cortex-M4F Processor