Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 8: QSSI Masked Interrupt Status (SSIMIS), offset 0x01C
The SSIMIS register is the masked interrupt status register. On a read, this register gives the current
masked status value of the corresponding interrupt. A write has no effect.
masked status value of the corresponding interrupt. A write has no effect.
QSSI Masked Interrupt Status (SSIMIS)
QSSI0 base: 0x4000.8000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x01C
Type RO, reset 0x0000.0000
QSSI1 base: 0x4000.9000
QSSI2 base: 0x4000.A000
QSSI3 base: 0x4000.B000
Offset 0x01C
Type RO, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RORMIS
RTMIS
RXMIS
TXMIS
DMARXMIS
DMATXMIS
EOTMIS
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
31:7
End of Transmit Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the transmission of
the last data bit.
the last data bit.
1
This bit is cleared when a 1 is written to the
EOTIC
bit in the SSI
Interrupt Clear (SSIICR) register.
0
RO
EOTMIS
6
QSSI Transmit DMA Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the completion of
the transmit DMA.
the transmit DMA.
1
This bit is cleared when a 1 is written to the
DMATXIC
bit in the SSI
Interrupt Clear (SSIICR) register.
0
RO
DMATXMIS
5
QSSI Receive DMA Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the completion of
the receive DMA.
the receive DMA.
1
This bit is cleared when a 1 is written to the
DMARXIC
bit in the SSI
Interrupt Clear (SSIICR) register.
0
RO
DMARXMIS
4
December 13, 2013
1406
Texas Instruments-Advance Information
Quad Synchronous Serial Interface (QSSI)