Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
QSSI Transmit FIFO Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the transmit FIFO
being half empty or less (if the
being half empty or less (if the
EOT
bit is clear) or due to the
transmission of the last data bit (if the
EOT
bit is set).
1
This bit is cleared when the transmit FIFO is more than half empty (if
the
the
EOT
bit is clear) or when it has any data in it (if the
EOT
bit is set).
0
RO
TXMIS
3
QSSI Receive FIFO Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the receive FIFO
being half full or more.
being half full or more.
1
This bit is cleared when the receive FIFO is less than half full.
0
RO
RXMIS
2
QSSI Receive Time-Out Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the receive time
out.
out.
1
This bit is cleared when a 1 is written to the
RTIC
bit in the SSI Interrupt
Clear (SSIICR) register.
0
RO
RTMIS
1
QSSI Receive Overrun Masked Interrupt Status
Description
Value
An interrupt has not occurred or is masked.
0
An unmasked interrupt was signaled due to the receive FIFO
overflowing.
overflowing.
1
This bit is cleared when a 1 is written to the
RORIC
bit in the SSI
Interrupt Clear (SSIICR) register.
0
RO
RORMIS
0
1407
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller