Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트

The FIFO Control Register can be programmed to control various aspects of the FIFO transaction,
such as RX and TX FIFO assignment, byte count value for FIFO triggers and flushing of the FIFOs.

I2C FIFO Control (I2CFIFOCTL)

I2C 0 base: 0x4002.0000
I2C 1 base: 0x4002.1000
I2C 2 base: 0x4002.2000
I2C 3 base: 0x4002.3000
I2C 4 base: 0x400C.0000
I2C 5 base: 0x400C.1000
I2C 6 base: 0x400C.2000
I2C 7 base: 0x400C.3000
I2C 8 base: 0x400B.8000
I2C 9 base: 0x400B.9000
Offset 0xF04
Type RW, reset 0x0004.0004

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

RXTRIG

reserved

DMARXENA

RXFLUSH

RXASGNMT

RW

RW

RW

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RW

RW

RW

Type

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

TXTRIG

reserved

DMATXENA

TXFLUSH

TXASGNMT

RW

RW

RW

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RW

RW

RW

Type

0

0

1

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset

Description

Reset

Type

Name

Bit/Field

RX Control Assignment

Description

Value

RX FIFO is assigned to Master

0

RX FIFO is assigned to Slave

1

0

RW

RXASGNMT

31

RX FIFO Flush

Setting this bit will Flush the RX FIFO. This bit will self-clear when the
flush has completed.

0

RW

RXFLUSH

30

DMA RX Channel Enable

Description

Value

DMA RX channel disabled

0

DMA RX channel enabled

1

0

RW

DMARXENA

29

Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0x00

RO

reserved

28:19