Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 7: Ethernet MAC Flow Control (EMACFLOWCTL), offset 0x018
The Ethernet MAC Flow Control (EMACFLOWCTL) register controls the generation and reception
of the control (pause command) frames by the MAC's Flow control module. A write to a register with
the
of the control (pause command) frames by the MAC's Flow control module. A write to a register with
the
FCBBPA
(bit 0) set to 1 triggers the Flow Control block to generate a pause control frame. The
fields of the control frame are selected as specified in the 802.3x specification, and the pause time
(
(
PT
) value from this register is used in the pause time field of the control frame. The
FCBBPA
bit is
cleared by the hardware once the control frame is transferred onto the cable. The Host must make
sure that the busy bit is clear before writing to the register.
sure that the busy bit is clear before writing to the register.
Ethernet MAC Flow Control (EMACFLOWCTL)
Base 0x400E.C000
Offset 0x018
Type RW, reset 0x0000.0000
Offset 0x018
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
PT
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
FCBBPA
TFE
RFE
UP
PLT
reserved
DZQP
reserved
RW
RW
RW
RW
RW
RW
RO
RW
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Pause Time
This field holds the value to be used in the pause time field in the transmit
control frame.
control frame.
For example, if these bits are set to 0x0100 then 256 slot times are used
in the Pause Time field in the transmit control frame.
in the Pause Time field in the transmit control frame.
0x0
RW
PT
31:16
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
15:8
Disable Zero-Quanta Pause
When this bit is set, it disables the automatic generation of the
Zero-Quanta Pause Control frames on the deassertion of the flow-control
signal from the FIFO layer. When this bit is reset, normal operation with
automatic Zero-Quanta Pause Control frame generation is enabled.
Zero-Quanta Pause Control frames on the deassertion of the flow-control
signal from the FIFO layer. When this bit is reset, normal operation with
automatic Zero-Quanta Pause Control frame generation is enabled.
Description
Value
Automatic Zero-Quanta Pause Control generation is enabled.
0
Automatic Zero-Quanta Pause Control generation is disabled.
1
0
RW
DZQP
7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0
RO
reserved
6
December 13, 2013
1678
Texas Instruments-Advance Information
Ethernet Controller