Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 54: Auxiliary Control (ACTLR), offset 0x008
Note:
This register can only be accessed from privileged mode.
The ACTLR register provides disable bits for
IT
folding, write buffer use for accesses to the default
memory map, and interruption of multi-cycle instructions. By default, this register is set to provide
optimum performance from the Cortex-M4 processor and does not normally require modification.
optimum performance from the Cortex-M4 processor and does not normally require modification.
Auxiliary Control (ACTLR)
Base 0xE000.E000
Offset 0x008
Type RW, reset 0x0000.0000
Offset 0x008
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
DISMCYC
DISWBUF
DISFOLD
reserved
DISFPCA
DISOOFP
reserved
RW
RW
RW
RO
RO
RO
RO
RO
RW
RW
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
31:10
Disable Out-Of-Order Floating Point
Disables floating-point instructions completing out of order with respect
to integer instructions.
to integer instructions.
0
RW
DISOOFP
9
Disable CONTROL.FPCA
Disable automatic update of the
FPCA
bit in the CONTROL register.
Important:
Two bits control when
FPCA
can be enabled: the
ASPEN
bit in the Floating-Point Context Control (FPCC)
register and the
register and the
DISFPCA
bit in the Auxiliary Control
(ACTLR) register.
0
RW
DISFPCA
8
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
7:3
Disable IT Folding
Description
Value
No effect.
0
Disables
IT
folding.
1
In some situations, the processor can start executing the first instruction
in an
in an
IT
block while it is still executing the
IT
instruction. This behavior
is called IT folding, and improves performance, However,
IT
folding can
cause jitter in looping. If a task must avoid jitter, set the
DISFOLD
bit
before executing the task, to disable
IT
folding.
0
RW
DISFOLD
2
December 13, 2013
174
Texas Instruments-Advance Information
Cortex-M4 Peripherals