Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Fast Auto-Negotiation Select Configuration
This bit is preconfigured at reset by the EMACPC register. For custom
configuration see “Initialization and Configuration” on page 1655.
configuration see “Initialization and Configuration” on page 1655.
Adjusting these bits reduces the time it takes to auto-negotiate between
two PHYs. In Fast AN mode, both PHYs should be configured to the
same configuration. These two bits define the duration for each state
of the auto-negotiation process according to the table above. The new
duration time must be enabled by setting bit 4 (
two PHYs. In Fast AN mode, both PHYs should be configured to the
same configuration. These two bits define the duration for each state
of the auto-negotiation process according to the table above. The new
duration time must be enabled by setting bit 4 (
FASTANEN
) of this
register.
Note:
Using this mode in cases where both link partners are not
configured to the same fast auto-negotiation configuration
might produce scenarios with unexpected behavior.
configured to the same fast auto-negotiation configuration
might produce scenarios with unexpected behavior.
Description
Value
Break Link Timer: 80 ms
Link Fail Inhibit Timer: 50 ms
Auto-Negate Wait Timer: 35 ms
0x0
Break Link Timer: 120 ms
Link Fail Inhibit Timer:75 ms
Auto-Negate Wait Timer: 50 ms
0x1
Break Link Timer: 240 ms
Link Fail Inhibit Timer:150 ms
Auto-Negate Wait Timer: 100 ms
0x2
reserved
0x3
0
RW
FANSEL
3:2
FAST RXDV Detection
Enabling this feature allows the PHY to pass data to the MII interface
earlier. This bit is set to disabled if using the EMACPC register bits to
program the PHY configuration.
earlier. This bit is set to disabled if using the EMACPC register bits to
program the PHY configuration.
Description
Value
Disable fast RXDV detection. The PHY operates in normal mode
where an internally asserted RXDV signal is sent to the MII
interface after detection of /J/K/.
where an internally asserted RXDV signal is sent to the MII
interface after detection of /J/K/.
0
An internal RXDV signal is asserted high on receive packet due
to detection of /J/ symbol only. Fast RXDV detection allows the
PHY to pass data to the MII interface earlier.
to detection of /J/ symbol only. Fast RXDV detection allows the
PHY to pass data to the MII interface earlier.
If a consecutive /K/ does not appear, RXERR is generated.
1
0
RW
FRXDVDET
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
0
December 13, 2013
1802
Texas Instruments-Advance Information
Ethernet Controller