Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 4: LCD LIDD CS0 Configuration (LIDDCS0CFG), offset 0x010
The LIDD CS0 Configuration (LIDDCS0CFG) register defines the timings for the read and write
strobes with respect to CS0.
strobes with respect to CS0.
LCD LIDD CS0 Configuration (LIDDCS0CFG)
Base 0x4405.0000
Offset 0x010
Type RW, reset 0x0044.0044
Offset 0x010
Type RW, reset 0x0044.0044
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RDSU
WRHOLD
WRDUR
WRSU
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
GAP
RDHOLD
RDDUR
RDSU
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Write Strobe (WR) Set-Up Cycles
When performing a write access, this field defines the number of MCLK
cycles that the LCDDATA bus, output enable, ADE, DIR and CS0 signals
have to be ready before the write strobe. The minimum value is 0x0.
cycles that the LCDDATA bus, output enable, ADE, DIR and CS0 signals
have to be ready before the write strobe. The minimum value is 0x0.
0x0
RW
WRSU
31:27
Write Strobe (WR) Duration Cycles
This field value defines the number of MCLK cycles for which the write
strobe is held active when performing a write access. The minimum
value is 0x1.
strobe is held active when performing a write access. The minimum
value is 0x1.
0x2
RW
WRDUR
26:21
Write Strobe (WR) Hold cycles.
This field value defines the number of MCLK cycles for which the
LCDDATA bus, output enable, ALE, DIR and CS0 signals are held after
the write strobe is deasserted when performing a write access. The
minimum value is 0x1.
LCDDATA bus, output enable, ALE, DIR and CS0 signals are held after
the write strobe is deasserted when performing a write access. The
minimum value is 0x1.
0x2
RW
WRHOLD
20:17
Read Strobe (RD) Set-Up cycles.
When performing a read access, this field defines the number of MCLK
cycles that the LCDDATA bus, output enable, ALE, DIR and CS0 signals
have to be ready before the read strobe is asserted.
cycles that the LCDDATA bus, output enable, ALE, DIR and CS0 signals
have to be ready before the read strobe is asserted.
0x0
RW
RDSU
16:12
Read Strobe (RD) Duration cycles.
This field defines the number of MCLK cycles for which the read strobe
is held active when performing a read access. The minimum value is
0x1.
is held active when performing a read access. The minimum value is
0x1.
0x1
RW
RDDUR
11:6
Read Strobe (RD) Hold cycles.
This field defines of MCLK cycles for which the LCDDATA bus, output
enable, ALE, DIR and CS0 signals are held after the read strobe is
deasserted when performing a read access. The minimum value is 0x1.
enable, ALE, DIR and CS0 signals are held after the read strobe is
deasserted when performing a read access. The minimum value is 0x1.
0x1
RW
RDHOLD
5:2
Field value defines the number of
LCDMCLK
cycles (GAP +1) between
the end of one CS0 (
LCDAC
) device access and the start of another CS0
(
LCDAC
) device access unless the two accesses are both reads. In this
case, this delay is not incurred. The minimum value is 0x0.
0x0
RW
GAP
1:0
December 13, 2013
1876
Texas Instruments-Advance Information
LCD Controller