Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 12: LCD Raster Timing 1 (LCDRASTRTIM1), offset 0x030
LCD Raster Timing 1 (LCDRASTRTIM1)
Base 0x4405.0000
Offset 0x030
Type RW, reset 0x0000.0000
Offset 0x030
Type RW, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
VFP
VBP
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
LPP
VSW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Vertical Back Porch
Value (from 0-255) use to specify the number of line clock periods to
add to the beginning of a frame before the first set of pixels is output to
the display. Note that line clock transitions during the insertion of the
extra line clock periods.
add to the beginning of a frame before the first set of pixels is output to
the display. Note that line clock transitions during the insertion of the
extra line clock periods.
0x00
RW
VBP
31:24
Vertical Front Porch
Value (from 0-255) used to specify the number of line clock periods to
add to the end of each frame. Note that the line clock transitions during
the insertion of the extra line clock periods.
add to the end of each frame. Note that the line clock transitions during
the insertion of the extra line clock periods.
0x00
RW
VFP
23:16
Vertical Sync Width Pulse
In active mode (
LCDTFT
=1), encoded value (from 1-64) used to specify
the number of line clock periods to set the lcd_fp pin active at the end
of each frame after the (vfp) period elapses. The number of clock cycles
is programmed value plus one. The frame clock is used as the VSYNC
signal in active mode.
of each frame after the (vfp) period elapses. The number of clock cycles
is programmed value plus one. The frame clock is used as the VSYNC
signal in active mode.
In passive mode (
LCDTFT
=0), encoded value (from 1-64) used to specify
the number of extra line clock periods to insert after the vertical front
porch (vfp) period has elapsed. Note that the width of lcd_fp is not
affected by vsw in passive mode and line clock transitions during the
insertion of the extra line clock periods (programmed value plus one).
porch (vfp) period has elapsed. Note that the width of lcd_fp is not
affected by vsw in passive mode and line clock transitions during the
insertion of the extra line clock periods (programmed value plus one).
0x00
RW
VSW
15:10
Lines Per Panel
Encoded value (programmed value range of {0:2047} represents an
actual range of {1:2048}) used to specify the number of lines per panel.
It represents the total number of lines on the LCD (programmed value
plus one). Bit 10 of this field is in LCDRASTRTIM2.
actual range of {1:2048}) used to specify the number of lines per panel.
It represents the total number of lines on the LCD (programmed value
plus one). Bit 10 of this field is in LCDRASTRTIM2.
0x00
RW
LPP
9:0
1887
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller