Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Instruction Bus Error
Description
Value
An instruction bus error has not occurred.
0
An instruction bus error has occurred.
1
The processor detects the instruction bus error on prefetching an
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
instruction, but sets this bit only if it attempts to issue the faulting
instruction.
When this bit is set, a fault address is not written to the FAULTADDR
register.
register.
This bit is cleared by writing a 1 to it.
0
RW1C
IBUS
8
Memory Management Fault Address Register Valid
Description
Value
The value in the Memory Management Fault Address
(MMADDR) register is not a valid fault address.
(MMADDR) register is not a valid fault address.
0
The MMADDR register is holding a valid fault address.
1
If a memory management fault occurs and is escalated to a hard fault
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
because of priority, the hard fault handler must clear this bit. This action
prevents problems if returning to a stacked active memory management
fault handler whose MMADDR register value has been overwritten.
This bit is cleared by writing a 1 to it.
0
RW1C
MMARV
7
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
6
Memory Management Fault on Floating-Point Lazy State Preservation
Description
Value
No memory management fault has occurred during floating-point
lazy state preservation.
lazy state preservation.
0
No memory management fault has occurred during floating-point
lazy state preservation.
lazy state preservation.
1
This bit is cleared by writing a 1 to it.
0
RW1C
MLSPERR
5
Stack Access Violation
Description
Value
No memory management fault has occurred on stacking for
exception entry.
exception entry.
0
Stacking for an exception entry has caused one or more access
violations.
violations.
1
When this bit is set, the SP is still adjusted but the values in the context
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
area on the stack might be incorrect. A fault address is not written to
the MMADDR register.
This bit is cleared by writing a 1 to it.
0
RW1C
MSTKE
4
December 13, 2013
198
Texas Instruments-Advance Information
Cortex-M4 Peripherals