Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 66: Hard Fault Status (HFAULTSTAT), offset 0xD2C
Note:
This register can only be accessed from privileged mode.
The HFAULTSTAT register gives information about events that activate the hard fault handler.
Bits are cleared by writing a 1 to them.
Hard Fault Status (HFAULTSTAT)
Base 0xE000.E000
Offset 0xD2C
Type RW1C, reset 0x0000.0000
Offset 0xD2C
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
FORCED
DBG
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW1C
RW1C
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
reserved
VECT
reserved
RO
RW1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Debug Event
This bit is reserved for Debug use. This bit must be written as a 0,
otherwise behavior is unpredictable.
otherwise behavior is unpredictable.
0
RW1C
DBG
31
Forced Hard Fault
Description
Value
No forced hard fault has occurred.
0
A forced hard fault has been generated by escalation of a fault
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
with configurable priority that cannot be handled, either because
of priority or because it is disabled.
1
When this bit is set, the hard fault handler must read the other fault
status registers to find the cause of the fault.
status registers to find the cause of the fault.
This bit is cleared by writing a 1 to it.
0
RW1C
FORCED
30
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
29:2
Vector Table Read Fault
Description
Value
No bus fault has occurred on a vector table read.
0
A bus fault occurred on a vector table read.
1
This error is always handled by the hard fault handler.
When this bit is set, the PC value stacked for the exception return points
to the instruction that was preempted by the exception.
to the instruction that was preempted by the exception.
This bit is cleared by writing a 1 to it.
0
RW1C
VECT
1
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0
RO
reserved
0
December 13, 2013
200
Texas Instruments-Advance Information
Cortex-M4 Peripherals