Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 11: QEI Interrupt Status and Clear (QEIISC), offset 0x028
This register provides the current set of interrupt sources that are asserted to the controller. If a bit
is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the
event in question has not occurred or is not enabled to generate an interrupt. This register is RW1C;
writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
is set, the latched event has occurred and is enabled to generate an interrupt; if a bit is clear the
event in question has not occurred or is not enabled to generate an interrupt. This register is RW1C;
writing a 1 to a bit position clears the bit and the corresponding interrupt reason.
QEI Interrupt Status and Clear (QEIISC)
QEI0 base: 0x4002.C000
Offset 0x028
Type RW1C, reset 0x0000.0000
Offset 0x028
Type RW1C, reset 0x0000.0000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
reserved
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
INTINDEX
INTTIMER
INTDIR
INTERROR
reserved
RW1C
RW1C
RW1C
RW1C
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x0000.000
RO
reserved
31:4
Phase Error Interrupt
Description
Value
No interrupt has occurred or the interrupt is masked.
0
The
INTERROR
bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
INTERROR
bit in the QEIRIS register.
0
RW1C
INTERROR
3
Direction Change Interrupt
Description
Value
No interrupt has occurred or the interrupt is masked.
0
The
INTDIR
bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
INTDIR
bit in the QEIRIS register.
0
RW1C
INTDIR
2
Velocity Timer Expired Interrupt
Description
Value
No interrupt has occurred or the interrupt is masked.
0
The
INTTIMER
bits in the QEIRIS register and the QEIINTEN
registers are set, providing an interrupt to the interrupt controller.
1
This bit is cleared by writing a 1. Clearing this bit also clears the
INTTIMER
bit in the QEIRIS register.
0
RW1C
INTTIMER
1
2031
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller