Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Table 32-39. EPI SDRAM Characteristics
Unit
Max
Nom
Min
Condition
Parameter Name
Parameter
ns
3
2
-
12-mA drive, C
L
= 30 pF
EPI Rise Time (from 20% to 80% of
V
V
DD
)
T
SDRAMR
ns
3
2
-
12-mA drive, C
L
= 30 pF
EPI Fall Time (from 80% to 20% of
V
V
DD
)
T
SDRAMF
Table 32-40. EPI SDRAM Interface Characteristics
a
Unit
Max
Nom
Min
Parameter Name
Parameter
Parameter No
ns
-
-
16.67
SDRAM Clock period
T
CK
E1
ns
-
-
8.33
SDRAM Clock high time
T
CH
E2
ns
-
-
8.33
SDRAM Clock low time
T
CL
E3
ns
4
-
-
CLK to output valid
T
COV
E4
ns
4
-
-
CLK to output invalid
T
COI
E5
ns
4
-
-
CLK to output tristate
T
COT
E6
ns
-
-
8.5
Input set up to CLK
T
S
E7
ns
-
-
0
CLK to input hold
T
H
E8
µs
-
-
100
Power-up time
T
PU
E9
ns
-
-
20
Precharge all banks
T
RP
E10
ns
-
-
66
Auto refresh
T
RFC
E11
EPI CLK
-
-
2
Program mode register
T
MRD
E12
a. The EPI SDRAM interface must use 12-mA drive.
Figure 32-18. SDRAM Initialization and Load Mode Register Timing
CLK
(EPI0S31)
CKE
(EPI0S30)
Command
(EPI0S[29:28,19:18])
DQMH, DQML
(EPI0S[17:16])
AD11, AD[9:0]
(EPI0S[11,9:0]
AD10
(EPI0S[10])
BAD[1:0]
(EPI0S[14:13])
AD [15,12]
(EPI0S [15,12])
NOP
PRE
NOP
AREF
NOP
PRE
NOP
AREF
NOP
LOAD
Code
All Banks
Single Bank
Code
Notes:
1. If CS is high at clock high time, all applied commands are NOP.
2. The Mode register may be loaded prior to the auto refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
2. The Mode register may be loaded prior to the auto refresh cycles if desired.
3. JEDEC and PC100 specify three clocks.
4. Outputs are guaranteed High-Z after command is issued.
E9
E10
E11
E12
E1
E2
E3
NOP
AREF
NOP
Active
Row
Row
Bank
December 13, 2013
2130
Texas Instruments-Advance Information
Electrical Characteristics