Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트

The DIVSCLK register specifies the source and divisor of the

DIVSCLK

reference clock output. This

signal can be used as a clock source to an external device but bears no timing relationship to other
signals.

The

DIVSCLK

signal output is not synchronized to the System Clock.

Divisor and Source Clock Configuration (DIVSCLK)

Base 0x400F.E000
Offset 0x148
Type RW, reset 0x0000.0000

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

SRC

reserved

EN

RW

RW

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RO

RW

Type

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

DIV

reserved

RW

RW

RW

RW

RW

RW

RW

RW

RO

RO

RO

RO

RO

RO

RO

RO

Type

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

0

Reset

Description

Reset

Type

Name

Bit/Field

DIVSCLK

Enable

This bit enables the generation of the

DIVSCLK

clock output. It resets

to 0 to disable the output thereby reducing initial current/power
consumption.

Description

Value

The clock output is disabled

0

Clock output is enabled.

1

0

RW

EN

31

Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0

RO

reserved

30:18

Clock Source

Selects the reference clock used to generate the output.

Description

Value

System Clock

0x0

PIOSC

0x1

MOSC

0x2

reserved

0x3

0

RW

SRC

17:16

Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.

0

RO

reserved

15:8