Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Register 4: Hibernation Control (HIBCTL), offset 0x010
This register is the control register for the Hibernation module. This register must be written last
before a hibernate event is issued. Writes to other registers after the
before a hibernate event is issued. Writes to other registers after the
HIBREQ
bit is set are not
guaranteed to complete before hibernation is entered.
Note:
Writes to this register have special timing requirements. Software should make use of the
WRC
bit in the HIBCTL register to ensure that the required synchronization has elapsed.
While the
WRC
bit is clear, any attempts to write this register are ignored. Reads may occur
at any time.
Note that once tamper is enabled, the following HIBCTL clock configuration bits and bus write stall
bit are locked and cannot be modified:
bit are locked and cannot be modified:
■
OSCSEL
■
OSCDRV
■
OSCBYP
■
VDD3ON
■
CLK32EN
■
RTCEN
Hibernation Control (HIBCTL)
Base 0x400F.C000
Offset 0x010
Type RW, reset 0x8000.2000
Offset 0x010
Type RW, reset 0x8000.2000
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
OSCBYP
OSCDRV
reserved
OSCSEL
reserved
RETCLR
WRC
RW
RW
RO
RW
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RW
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
Reset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
RTCEN
HIBREQ
reserved
RTCWEN
PINWEN
reserved
CLK32EN
VABORT
VDD3ON
BATWKEN
BATCHK
reserved
VBATSEL
reserved
RW
RW
RO
RW
RW
RO
RW
RW
RW
RW
RW
RO
RO
RW
RW
RO
Type
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
Reset
Description
Reset
Type
Name
Bit/Field
Write Complete/Capable
Description
Value
The interface is processing a prior write and is busy. Any write
operation that is attempted while
operation that is attempted while
WRC
is 0 results in
undetermined behavior.
0
The interface is ready to accept a write.
1
Software must poll this bit between write requests and defer writes until
WRC
=1 to ensure proper operation. An interrupt can be configured to
indicate the WRC has completed.
The bit name
WRC
means "Write Complete," which is the normal use of
the bit (between write accesses). However, because the bit is set
out-of-reset, the name can also mean "Write Capable" which simply
indicates that the interface may be written to by software. This difference
may be exploited by software at reset time to detect which method of
programming is appropriate: 0 = software delay loops required; 1 =
out-of-reset, the name can also mean "Write Capable" which simply
indicates that the interface may be written to by software. This difference
may be exploited by software at reset time to detect which method of
programming is appropriate: 0 = software delay loops required; 1 =
WRC
paced available.
1
RO
WRC
31
587
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller