Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Table 11-12. EPI General-Purpose Signal Connections (continued)
General- Purpose
Signal (D32)
General- Purpose
Signal (D24, A4)
General- Purpose
Signal (D16, A12)
General-Purpose
Signal (D8, A20)
EPI Signal
D21
D21
A5
A13
EPI0S21
D22
D22
A6
A14
EPI0S22
D23
D23
A7
A15
EPI0S23
D24
A0
b
A8
A16
EPI0S24
D25
A1
A9
A17
EPI0S25
D26
A2
A10
A18
EPI0S26
D27
A3
A11
A19
EPI0S27
D28
WR
WR
WR
EPI0S28
D29
RD
RD
RD
EPI0S29
D30
Frame
Frame
Frame
EPI0S30
D31
Clock
Clock
Clock
EPI0S31
a. In this mode, half-word accesses are used. AO is the LSB of the address and is equivalent to the system A1 address.
b. In this mode, word accesses are used. AO is the LSB of the address and is equivalent to the system A2 address.
11.4.4.1
Bus Operation
A basic access is 1 EPI clock for write cycles and 2 EPI clocks for read cycles. An additional EPI
clock can be inserted into a write cycle by setting the
clock can be inserted into a write cycle by setting the
WR2CYC
bit in the EPIGPCFG register.
Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0
Data
Clock
(EPI0S31)
Frame
(EPI0S30)
RD
(EPI0S29)
WR
(EPI0S28)
Address
Data
881
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller