Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
![Texas Instruments](https://files.manualsbrain.com/attachments/b46f99d826b2b0e0e5f558c5fb6483942eb9216b/common/fit/150/50/c15ea36eb1fb1cce99a3b94668675bfc78ce832d8d727d9a7bb51a125510/brand_logo.gif)
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
Clock Gated
Description
Value
The EPI clock is free running.
0
The EPI clock is held low.
1
Note:
A software application should only set the
CLKGATE
bit when
there are no pending transfers or no EPI register access has
been issued.
been issued.
0
RW
CLKGATE
31
Clock Gated Idle
Description
Value
The EPI clock is free running.
0
The EPI clock is output only when there is data to write or read
(current transaction); otherwise the EPI clock is held low.
(current transaction); otherwise the EPI clock is held low.
1
Note that
EPI0S32
is an iRDY signal if
RDYEN
is set.
CLKGATEI
is
ignored if
CLKPIN
is 0 or if the
COUNT0
field in the EPIBAUD register
is cleared.
0
RW
CLKGATEI
30
Invert Output Clock Enable
Note:
If operating in asynchronous mode,
CLKINV
must be 0.
Description
Value
No effect.
0
Invert EPI clock to ensure the rising edge is centered for
outbound signal's setup and hold. Inbound signal is captured
on rising edge EPI clock.
outbound signal's setup and hold. Inbound signal is captured
on rising edge EPI clock.
1
0
RW
CLKINV
29
Input Ready Enable
Description
Value
No effect.
0
An external ready (iRDY) can be used to control the continuation
of the current access. If this bit is set and the iRDY signal
(
of the current access. If this bit is set and the iRDY signal
(
EPIS032
) is low, the current access is stalled.
1
0
RW
RDYEN
28
Input Ready Invert
Description
Value
No effect.
0
Invert polarity of incoming external ready. If this bit is set and
the iRDY signal (
the iRDY signal (
EPIS032
) is high the current access is stalled.
1
0
RW
IRDYINV
27
Software should not rely on the value of a reserved bit. To provide
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
compatibility with future products, the value of a reserved bit should be
preserved across a read-modify-write operation.
0x00
RO
reserved
26:24
December 13, 2013
902
Texas Instruments-Advance Information
External Peripheral Interface (EPI)