Texas Instruments Development Kit for TM4C129x,Tiva™ ARM® Cortex™ -M4 Microcontroller DK-TM4C129X DK-TM4C129X 데이터 시트
제품 코드
DK-TM4C129X
Description
Reset
Type
Name
Bit/Field
External FIFO FULL Enable
Description
Value
No effect.
0
An external FIFO full signal can be used to control write cycles.
If this bit is set and the FFULL signal is high, XFIFO writes are
stalled.
If this bit is set and the FFULL signal is high, XFIFO writes are
stalled.
1
0
RW
XFFEN
23
External FIFO EMPTY Enable
Description
Value
No effect.
0
An external FIFO empty signal can be used to control read
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
cycles. If this bit is set and the FEMPTY signal is high, XFIFO
reads are stalled.
1
0
RW
XFEEN
22
WRITE Strobe Polarity
Description
Value
The WRITE strobe for CS0n is WRn (active Low).
0
The WRITE strobe for CS0n is WR (active High).
1
0
RW
WRHIGH
21
READ Strobe Polarity
Description
Value
The READ strobe for CS0n is RDn (active Low).
0
The READ strobe for CS0n is RD (active High).
1
0
RW
RDHIGH
20
ALE Strobe Polarity
Description
Value
The address latch strobe for CS0n is ALEn (active Low).
0
The address latch strobe for CS0n is ALE (active High).
1
1
RW
ALEHIGH
19
PSRAM Configuration Register Write
Used for PSRAM configuration registers.
With
WRCRE
set, the next transaction by the EPI will be a write of the
CR
bit field in the EPIHBPSRAM register to the configuration register (CR)
of the PSRAM. The
of the PSRAM. The
WRCRE
bit will self clear once the write-enabled CRE
access is complete.
Description
Value
No Action.
0
Start CRE write transaction for CS0n.
1
0
RW
WRCRE
18
903
December 13, 2013
Texas Instruments-Advance Information
Tiva
™
TM4C129XNCZAD Microcontroller