Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-92. Timings for ATA Module — Ultra DMA AC Timing
(see
through
) (continued)
-1G
NO.
UNIT
MODE
MIN
MAX
0
230
ns
1
200
ns
2
170
ns
14
t
FS
First STROBE time
3
130
ns
4
120
ns
5
90
ns
0-2
0
150
ns
15
t
LI
Limited interlock time
3-4
0
100
ns
5
0
75
ns
16
t
MLI
Interlock time with minimum
0-5
20
ns
17
t
UI
Unlimited interlock time
0-5
0
ns
Maximum time allowed for output drivers to
18
t
AZ
0-5
10
ns
release
19
t
ZAH
Minimum delay time required for output
0-5
20
ns
Minimum delay time for driver to assert or negate
20
t
ZAD
0-5
0
ns
(from released)
Envelope time, DMACK to STOP and DMACK to
21
t
ENV
HDMARDY during in-burst initiation and from
0-5
(TENV + 1)P - 0.5
(TENV + 1)P + 1.4
ns
DMACK to STOP during data out burst initiation
0
75
ns
1
70
ns
22
t
RFS
Ready-to-final-STROBE time
2-4
60
ns
5
50
ns
Ready to pause time, (HDMARDY (DIOR) to
0-5
(UDMATRP + 1)P - 0.8
ns
STOP (DIOW))
0
160
ns
23
t
RP
1
125
ns
Ready to pause time, (DDMARDY (IORDY) to
DMARQ)
DMARQ)
2-4
100
ns
5
85
ns
24
t
IORDYZ
Maximum time before releasing IORDY
0-5
20
ns
25
t
ZIORDY
Minimum time before driving IORDY
0-5
0
ns
Setup and hold time for DMACK (before
26
t
ACK
0-5
20
ns
assertion or negation)
STROBE edge to negation of DMARQ or
27
t
SS
assertion of STOP (when sender terminates a
0-5
50
ns
burst)
286
Peripheral Information and Electrical Specifications
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