Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
t
2CYC
t
DH
t
DS
t
DH
t
DS
t
DH
DSTROBE
(IORDY)
DD[15:0]
t
CYC
(A)
t
CYC
(A)
DMARQ
t
DVH
t
ENV
DSTROBE (IORDY)
(A)
STOP (DIOW)
(A)
HDMARDY (DIOR)
(A)
DD[15:0]
DA[2:0],
ATA_CS0,
ATA_CS1
t
FS
t
ENV
t
ZFS
t
DZFS
t
DVS
t
ZAD
t
ZAD
t
FS
t
UI
t
ACK
t
ACK
t
ZIORDY
t
AZ
t
ACK
DMACK
SPRS605C – JULY 2009 – REVISED JUNE 2012
A.
The definitions for the DIOW:STOP, DIOR:HDMARDY, and IORDY:DSTROBE signal lines are not in effect until
DMARQ and DMACK are asserted.
DMARQ and DMACK are asserted.
Figure 7-66. ATA Initiating an Ultra DMA Data-In Burst Timing
A.
While DSTROBE (IORDY) timing is t
CYC
at the device, it may be different at the host due to propagation delay
differences on the cable.
Figure 7-67. ATA Sustained Ultra DMA Data-In Data Transfer Timing
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Peripheral Information and Electrical Specifications
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