Texas Instruments DM6467 Digital Video Evaluation Module TMDXEVM6467T TMDXEVM6467T 데이터 시트
제품 코드
TMDXEVM6467T
SPRS605C – JULY 2009 – REVISED JUNE 2012
Table 7-111. General Input Timing Requirements in Master Mode
-1G
NO.
UNIT
MIN
MAX
Setup time, SPI_SOMI valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
SPI_CLK, 3-/4-/5-pin mode,
4
polarity = 0, phase = 0
Setup time, SPI_SOMI valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
SPI_CLK, 3-/4-/5-pin mode,
4
polarity = 0, phase = 1
7
t
su(SOMI-CLK)
ns
Setup time, SPI_SOMI valid before receive rising edge of
SPI_CLK, 3-/4-/5-pin mode,
SPI_CLK, 3-/4-/5-pin mode,
4
polarity = 1, phase = 0
Setup time, SPI_SOMI valid before receive falling edge of
SPI_CLK, 3-/4-/5-pin mode,
SPI_CLK, 3-/4-/5-pin mode,
4
polarity = 1, phase = 1
Hold time, SPI_SOMI valid after receive falling edge of SPI_CLK,
2
3-/4-/5-pin mode, polarity = 0, phase = 0
Hold time, SPI_SOMI valid after receive rising edge of SPI_CLK, 3-
2
/4-/5-pin mode, polarity = 0, phase = 1
8
t
h(CLK-SOMI)
ns
Hold time, SPI_SOMI valid after receive rising edge of SPI_CLK, 3-
2
/4-/5-pin mode, polarity = 1, phase = 0
Hold time, SPI_SOMI valid after receive falling edge of SPI_CLK,
2
3-/4-/5-pin mode, polarity = 1, phase = 1
Copyright © 2009–2012, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
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