Texas Instruments CC2650DK 사용자 설명서
UART
DMA Channel 2 SREQ
DMA
DMA done CH2
DMA done CH1
DMA Channel 2 REQ
DMA active CH2
DMA Channel 1 SREQ
DMA Channel 1 REQ
DMA active CH1
Event
UART0_TX_DMASREQ
UART0_TX_DMABREQ
DMA RX Clear
DMA TX Clear
DMA Channel 14 REQ
UART0_TX_DMASREQ
UART0_TX_DMABREQ
UART Interrupt
Controller
UART DMA
Controller
UART Interrupt
CPU
Initialization and Configuration
Figure 19-3. µDMA Example
19.6 Initialization and Configuration
The UART module provides four I/O signals to be routed to the pads. The following signals are selected
through the [IOCFGxx] registers in the IOC module.
through the [IOCFGxx] registers in the IOC module.
The UART module provides four I/O functions to be routed to the pads:
•
Inputs: RXD, CTS
•
Outputs: TXD, RTS
CTS and RTS lines are active low.
NOTE:
IOC must be configured before enabling UART, or unwanted transitions on input signals may
confuse UART on incoming transactions. When IOC is configured as UART-specific I/Os
(RXD, CTS, TXD, or RTS), IOC sets static output driver enable to the pad (output driver
enable = 1 for output TXD and RTS and output driver enable = 0 for inputs RXD and CTS).
(RXD, CTS, TXD, or RTS), IOC sets static output driver enable to the pad (output driver
enable = 1 for output TXD and RTS and output driver enable = 0 for inputs RXD and CTS).
1334
Universal Asynchronous Receivers and Transmitters (UARTS)
SWCU117A – February 2015 – Revised March 2015
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