Texas Instruments CC2650DK 사용자 설명서
UARTS Registers
19.7.1.1 DR Register (Offset = 0h) [reset = X]
DR is shown in
and described in
Data For words to be transmitted: - if the FIFOs are enabled (LCRH.FEN = 1), data written to this location
is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the
transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates
transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit
(if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the
FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun)
is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte
and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data byte is read by performing reads from this register along with the corresponding status information.
The status information can also be read by a read of the RSR register.
is pushed onto the transmit FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), data is stored in the
transmitter holding register (the bottom word of the transmit FIFO). The write operation initiates
transmission from the UART. The data is prefixed with a start bit, appended with the appropriate parity bit
(if parity is enabled), and a stop bit. The resultant word is then transmitted. For received words: - if the
FIFOs are enabled (LCRH.FEN = 1), the data byte and the 4-bit status (break, frame, parity, and overrun)
is pushed onto the 12-bit wide receive FIFO - if the FIFOs are not enabled (LCRH.FEN = 0), the data byte
and status are stored in the receiving holding register (the bottom word of the receive FIFO). The received
data byte is read by performing reads from this register along with the corresponding status information.
The status information can also be read by a read of the RSR register.
Figure 19-4. DR Register
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESERVED
R-X
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESERVED
OE
BE
PE
FE
DATA
R-X
R-0h
R-0h
R-0h
R-0h
R/W-0h
Table 19-4. DR Register Field Descriptions
Bit
Field
Type
Reset
Description
31-12
RESERVED
R
X
Software should not rely on the value of a reserved. Writing any
other value than the reset value may result in undefined behavior.
other value than the reset value may result in undefined behavior.
11
OE
R
0h
UART Overrun Error: This bit is set to 1 if data is received and the
receive FIFO is already full. The FIFO contents remain valid because
no more data is written when the FIFO is full, , only the contents of
the shift register are overwritten. This is cleared to 0 once there is an
empty space in the FIFO and a new character can be written to it.
receive FIFO is already full. The FIFO contents remain valid because
no more data is written when the FIFO is full, , only the contents of
the shift register are overwritten. This is cleared to 0 once there is an
empty space in the FIFO and a new character can be written to it.
10
BE
R
0h
UART Break Error: This bit is set to 1 if a break condition was
detected, indicating that the received data input (UARTRXD input
pin) was held LOW for longer than a full-word transmission time
(defined as start, data, parity and stop bits). In FIFO mode, this error
is associated with the character at the top of the FIFO (i.e., the
oldest received data character since last read). When a break
occurs, a 0 character is loaded into the FIFO. The next character is
enabled after the receive data input (UARTRXD input pin) goes to a
1 (marking state), and the next valid start bit is received.
detected, indicating that the received data input (UARTRXD input
pin) was held LOW for longer than a full-word transmission time
(defined as start, data, parity and stop bits). In FIFO mode, this error
is associated with the character at the top of the FIFO (i.e., the
oldest received data character since last read). When a break
occurs, a 0 character is loaded into the FIFO. The next character is
enabled after the receive data input (UARTRXD input pin) goes to a
1 (marking state), and the next valid start bit is received.
9
PE
R
0h
UART Parity Error: When set to 1, it indicates that the parity of the
received data character does not match the parity that the
LCRH.EPS and LCRH.SPS select. In FIFO mode, this error is
associated with the character at the top of the FIFO (i.e., the oldest
received data character since last read).
received data character does not match the parity that the
LCRH.EPS and LCRH.SPS select. In FIFO mode, this error is
associated with the character at the top of the FIFO (i.e., the oldest
received data character since last read).
8
FE
R
0h
UART Framing Error: When set to 1, it indicates that the received
character did not have a valid stop bit (a valid stop bit is 1). In FIFO
mode, this error is associated with the character at the top of the
FIFO (i.e., the oldest received data character since last read).
character did not have a valid stop bit (a valid stop bit is 1). In FIFO
mode, this error is associated with the character at the top of the
FIFO (i.e., the oldest received data character since last read).
7-0
DATA
R/W
0h
Data transmitted or received: On writes, the transmit data character
is pushed into the FIFO. On reads, the oldest received data
character since the last read is returned.
is pushed into the FIFO. On reads, the oldest received data
character since the last read is returned.
1337
SWCU117A – February 2015 – Revised March 2015
Universal Asynchronous Receivers and Transmitters (UARTS)
Copyright © 2015, Texas Instruments Incorporated